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50 lines
1.2 KiB
YAML
50 lines
1.2 KiB
YAML
# RUN: llc -march=hexagon -run-pass expand-condsets -o - %s -verify-machineinstrs -debug-only=expand-condsets 2>&1 | FileCheck %s
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# REQUIRES: asserts
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# Check that coalesced registers are removed from live intervals.
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#
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# Check that vreg3 is coalesced into vreg4, and that after coalescing
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# it is no longer in live intervals.
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# CHECK-LABEL: After expand-condsets
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# CHECK: INTERVALS
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# CHECK-NOT: vreg3
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# CHECK: MACHINEINSTRS
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--- |
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define void @fred() { ret void }
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...
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---
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name: fred
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tracksRegLiveness: true
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registers:
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- { id: 0, class: intregs }
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- { id: 1, class: intregs }
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- { id: 2, class: predregs }
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- { id: 3, class: intregs }
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- { id: 4, class: intregs }
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liveins:
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- { reg: '%r0', virtual-reg: '%0' }
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- { reg: '%r1', virtual-reg: '%1' }
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- { reg: '%p0', virtual-reg: '%2' }
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body: |
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bb.0:
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liveins: %r0, %r1, %p0
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%0 = COPY %r0
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%0 = COPY %r0 ; Force isSSA = false.
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%1 = COPY %r1
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%2 = COPY %p0
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; Check that %3 was coalesced into %4.
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; CHECK: %4 = A2_abs %1
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; CHECK: %4 = A2_tfrt killed %2, killed %0, implicit %4
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%3 = A2_abs %1
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%4 = C2_mux %2, %0, %3
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%r0 = COPY %4
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J2_jumpr %r31, implicit %r0, implicit-def %pc
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...
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