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llvm-mirror/test/CodeGen/Hexagon/idxload-with-zero-offset.ll
David Blaikie ab043ff680 [opaque pointer type] Add textual IR support for explicit type parameter to load instruction
Essentially the same as the GEP change in r230786.

A similar migration script can be used to update test cases, though a few more
test case improvements/changes were required this time around: (r229269-r229278)

import fileinput
import sys
import re

pat = re.compile(r"((?:=|:|^)\s*load (?:atomic )?(?:volatile )?(.*?))(| addrspace\(\d+\) *)\*($| *(?:%|@|null|undef|blockaddress|getelementptr|addrspacecast|bitcast|inttoptr|\[\[[a-zA-Z]|\{\{).*$)")

for line in sys.stdin:
  sys.stdout.write(re.sub(pat, r"\1, \2\3*\4", line))

Reviewers: rafael, dexonsmith, grosser

Differential Revision: http://reviews.llvm.org/D7649

llvm-svn: 230794
2015-02-27 21:17:42 +00:00

71 lines
2.0 KiB
LLVM

; RUN: llc -march=hexagon < %s | FileCheck %s
; Check that we generate load instruction with (base + register offset << x)
; load word
define i32 @load_w(i32* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memw(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#2)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i32, i32* %a, i32 %tmp
%val = load i32, i32* %scevgep9, align 4
ret i32 %val
}
; load unsigned half word
define i16 @load_uh(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memuh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i16, i16* %a, i32 %tmp
%val = load i16, i16* %scevgep9, align 2
ret i16 %val
}
; load signed half word
define i32 @load_h(i16* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memh(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#1)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i16, i16* %a, i32 %tmp
%val = load i16, i16* %scevgep9, align 2
%conv = sext i16 %val to i32
ret i32 %conv
}
; load unsigned byte
define i8 @load_ub(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memub(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<#0)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i8, i8* %a, i32 %tmp
%val = load i8, i8* %scevgep9, align 1
ret i8 %val
}
; load signed byte
define i32 @foo_2(i8* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}{{ *}}={{ *}}memb(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#0)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i8, i8* %a, i32 %tmp
%val = load i8, i8* %scevgep9, align 1
%conv = sext i8 %val to i32
ret i32 %conv
}
; load doubleword
define i64 @load_d(i64* nocapture %a, i32 %n, i32 %m) nounwind {
; CHECK: r{{[0-9]+}}:{{[0-9]+}}{{ *}}={{ *}}memd(r{{[0-9]+}}{{ *}}+{{ *}}r{{[0-9]+}}{{ *}}<<{{ *}}#3)
entry:
%tmp = add i32 %n, %m
%scevgep9 = getelementptr i64, i64* %a, i32 %tmp
%val = load i64, i64* %scevgep9, align 8
ret i64 %val
}