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49b7f76310
Summary: On Linux, /usr/include/bits/byteswap-16.h defines __byteswap_16(x) as an inlined LRVH (Load Reversed Half-word) instruction. The SystemZ back-end did not support this opcode and the inlined assembly would cause a fatal error. Reviewers: bryanpkc, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18732 llvm-svn: 269688
101 lines
2.7 KiB
LLVM
101 lines
2.7 KiB
LLVM
; Test 32-bit byteswaps from registers to memory.
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;
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; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s
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declare i16 @llvm.bswap.i16(i16 %a)
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; Check STRVH with no displacement.
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define void @f1(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f1:
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; CHECK: strvh %r3, 0(%r2)
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; CHECK: br %r14
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%dst
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ret void
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}
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; Check the high end of the aligned STRVH range.
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define void @f2(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f2:
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; CHECK: strvh %r3, 524286(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%dst, i64 262143
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check the next word up, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f3(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f3:
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; CHECK: agfi %r2, 524288
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; CHECK: strvh %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%dst, i64 262144
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check the high end of the negative aligned STRVH range.
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define void @f4(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f4:
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; CHECK: strvh %r3, -2(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%dst, i64 -1
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check the low end of the STRVH range.
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define void @f5(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f5:
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; CHECK: strvh %r3, -524288(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%dst, i64 -262144
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check the next word down, which needs separate address logic.
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; Other sequences besides this one would be OK.
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define void @f6(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f6:
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; CHECK: agfi %r2, -524290
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; CHECK: strvh %r3, 0(%r2)
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; CHECK: br %r14
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%ptr = getelementptr i16, i16 *%dst, i64 -262145
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check that STRVH allows an index.
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define void @f7(i64 %src, i64 %index, i16 %a) {
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; CHECK-LABEL: f7:
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; CHECK: strvh %r4, 524287({{%r3,%r2|%r2,%r3}})
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; CHECK: br %r14
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%add1 = add i64 %src, %index
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%add2 = add i64 %add1, 524287
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%ptr = inttoptr i64 %add2 to i16 *
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store i16 %swapped, i16 *%ptr
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ret void
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}
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; Check that volatile stores do not use STRVH, which might access the
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; storage multple times.
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define void @f8(i16 *%dst, i16 %a) {
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; CHECK-LABEL: f8:
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; CHECK: lrvr [[REG:%r[0-5]]], %r3
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; CHECK: srl [[REG]], 16
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; CHECK: sth [[REG]], 0(%r2)
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; CHECK: br %r14
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%swapped = call i16 @llvm.bswap.i16(i16 %a)
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store volatile i16 %swapped, i16 *%dst
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ret void
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}
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