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9f833b6097
MachineFunctionProperties represents a set of properties that a MachineFunction can have at particular points in time. Existing examples of this idea are MachineRegisterInfo::isSSA() and MachineRegisterInfo::tracksLiveness() which will eventually be switched to use this mechanism. This change introduces the AllVRegsAllocated property; i.e. the property that all virtual registers have been allocated and there are no VReg operands left. With this mechanism, passes can declare that they require a particular property to be set, or that they set or clear properties by implementing e.g. MachineFunctionPass::getRequiredProperties(). The MachineFunctionPass base class verifies that the requirements are met, and handles the setting and clearing based on the delcarations. Passes can also directly query and update the current properties of the MF if they want to have conditional behavior. This change annotates the target-independent post-regalloc passes; future changes will also annotate target-specific ones. Reviewers: qcolombet, hfinkel Differential Revision: http://reviews.llvm.org/D18421 llvm-svn: 264593
60 lines
2.0 KiB
C++
60 lines
2.0 KiB
C++
//===-- FuncletLayout.cpp - Contiguously lay out funclets -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements basic block placement transformations which result in
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// funclets being contiguous.
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//
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//===----------------------------------------------------------------------===//
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#include "llvm/CodeGen/Passes.h"
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#include "llvm/CodeGen/Analysis.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "funclet-layout"
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namespace {
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class FuncletLayout : public MachineFunctionPass {
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public:
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static char ID; // Pass identification, replacement for typeid
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FuncletLayout() : MachineFunctionPass(ID) {
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initializeFuncletLayoutPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &F) override;
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MachineFunctionProperties getRequiredProperties() const override {
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return MachineFunctionProperties().set(
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MachineFunctionProperties::Property::AllVRegsAllocated);
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}
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};
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}
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char FuncletLayout::ID = 0;
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char &llvm::FuncletLayoutID = FuncletLayout::ID;
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INITIALIZE_PASS(FuncletLayout, "funclet-layout",
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"Contiguously Lay Out Funclets", false, false)
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bool FuncletLayout::runOnMachineFunction(MachineFunction &F) {
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DenseMap<const MachineBasicBlock *, int> FuncletMembership =
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getFuncletMembership(F);
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if (FuncletMembership.empty())
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return false;
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F.sort([&](MachineBasicBlock &X, MachineBasicBlock &Y) {
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auto FuncletX = FuncletMembership.find(&X);
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auto FuncletY = FuncletMembership.find(&Y);
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assert(FuncletX != FuncletMembership.end());
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assert(FuncletY != FuncletMembership.end());
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return FuncletX->second < FuncletY->second;
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});
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// Conservatively assume we changed something.
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return true;
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}
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