mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-19 11:02:59 +02:00
10839866a1
This patch implements initial backend support for a -mtune CPU controlled by a "tune-cpu" function attribute. If the attribute is not present X86 will use the resolved CPU from target-cpu attribute or command line. This patch adds MC layer support a tune CPU. Each CPU now has two sets of features stored in their GenSubtargetInfo.inc tables . These features lists are passed separately to the Processor and ProcessorModel classes in tablegen. The tune list defaults to an empty list to avoid changes to non-X86. This annoyingly increases the size of static tables on all target as we now store 24 more bytes per CPU. I haven't quantified the overall impact, but I can if we're concerned. One new test is added to X86 to show a few tuning features with mismatched tune-cpu and target-cpu/target-feature attributes to demonstrate independent control. Another new test is added to demonstrate that the scheduler model follows the tune CPU. I have not added a -mtune to llc/opt or MC layer command line yet. With no attributes we'll just use the -mcpu for both. MC layer tools will always follow the normal CPU for tuning. Differential Revision: https://reviews.llvm.org/D85165
65 lines
1.9 KiB
C++
65 lines
1.9 KiB
C++
//===- TargetSubtargetInfo.cpp - General Target Information ----------------==//
|
|
//
|
|
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
|
|
// See https://llvm.org/LICENSE.txt for license information.
|
|
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file This file describes the general parts of a Subtarget.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "llvm/CodeGen/TargetSubtargetInfo.h"
|
|
|
|
using namespace llvm;
|
|
|
|
TargetSubtargetInfo::TargetSubtargetInfo(
|
|
const Triple &TT, StringRef CPU, StringRef TuneCPU, StringRef FS,
|
|
ArrayRef<SubtargetFeatureKV> PF, ArrayRef<SubtargetSubTypeKV> PD,
|
|
const MCWriteProcResEntry *WPR, const MCWriteLatencyEntry *WL,
|
|
const MCReadAdvanceEntry *RA, const InstrStage *IS, const unsigned *OC,
|
|
const unsigned *FP)
|
|
: MCSubtargetInfo(TT, CPU, TuneCPU, FS, PF, PD, WPR, WL, RA, IS, OC, FP) {}
|
|
|
|
TargetSubtargetInfo::~TargetSubtargetInfo() = default;
|
|
|
|
bool TargetSubtargetInfo::enableAtomicExpand() const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableIndirectBrExpand() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableMachineScheduler() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableJoinGlobalCopies() const {
|
|
return enableMachineScheduler();
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableRALocalReassignment(
|
|
CodeGenOpt::Level OptLevel) const {
|
|
return true;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enableAdvancedRASplitCost() const {
|
|
return false;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enablePostRAScheduler() const {
|
|
return getSchedModel().PostRAScheduler;
|
|
}
|
|
|
|
bool TargetSubtargetInfo::enablePostRAMachineScheduler() const {
|
|
return enableMachineScheduler() && enablePostRAScheduler();
|
|
}
|
|
|
|
bool TargetSubtargetInfo::useAA() const {
|
|
return false;
|
|
}
|
|
|
|
void TargetSubtargetInfo::mirFileLoaded(MachineFunction &MF) const { }
|