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95 lines
3.9 KiB
TableGen
95 lines
3.9 KiB
TableGen
//==- HexagonAlias.td - Hexagon Instruction Aliases ---------*- tablegen -*-==//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Hexagon Instruction Mappings
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//===----------------------------------------------------------------------===//
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// V6_vassignp: Vector assign mapping.
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let hasNewValue = 1, opNewValue = 0, isAsmParserOnly = 1 in
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def HEXAGON_V6_vassignpair: CVI_VA_DV_Resource <
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(outs VecDblRegs:$Vdd),
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(ins VecDblRegs:$Vss),
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"$Vdd = $Vss">;
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// maps Vd = #0 to Vd = vxor(Vd, Vd)
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def : InstAlias<"$Vd = #0",
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(V6_vxor VectorRegs:$Vd, VectorRegs:$Vd, VectorRegs:$Vd)>,
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Requires<[HasV60T]>;
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// maps Vdd = #0 to Vdd = vsub(Vdd, Vdd)
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def : InstAlias<"$Vdd = #0",
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(V6_vsubw_dv VecDblRegs:$Vdd, VecDblRegs:$Vdd, VecDblRegs:$Vdd)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd = vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd &= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd |= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)" -> "$Qd ^= vcmp.eq($Vu.h, $Vv.h)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.uh, $Vv.uh)",
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(V6_veqh_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd = vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd &= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd |= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqh_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)" -> "$Qd ^= vcmp.eq($Vu.w, $Vv.w)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.uw, $Vv.uw)",
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(V6_veqw_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd = vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd = vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd = vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd &= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd &= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd &= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_and VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd |= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd |= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd |= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_or VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)" -> "$Qd ^= vcmp.eq($Vu.b, $Vv.b)"
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def : InstAlias<"$Qd ^= vcmp.eq($Vu.ub, $Vv.ub)",
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(V6_veqb_xor VecPredRegs:$Qd, VectorRegs:$Vu, VectorRegs:$Vv)>,
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Requires<[HasV60T]>;
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// maps "$Rd.w = vextract($Vu, $Rs)" -> "$Rd = vextract($Vu, $Rs)"
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def : InstAlias<"$Rd.w = vextract($Vu, $Rs)",
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(V6_extractw IntRegs:$Rd, VectorRegs:$Vu, IntRegs:$Rs)>,
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Requires<[HasV60T]>;
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