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dd3a0683bf
Summary: SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a BR_JT opcode. While many backends optimize this multiply into a shift, e.g. the MIPS backend currently always lowers this into a sequence of load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv(). I initially changed the multiply to a shift in the MIPS backend but it turns out that would not have handled the MIPSR6 case and was a lot more code than doing it in LegalizeDAG. I believe performing this simple optimization in LegalizeDAG instead of each individual backend is the better solution since this also fixes other backeds such as MSP430 which calls the multiply runtime function __mspabi_mpyi without this patch. Reviewers: sdardis, atanasyan, pftbest, asl Reviewed By: sdardis Subscribers: llvm-commits Differential Revision: https://reviews.llvm.org/D45760 llvm-svn: 332439
95 lines
3.1 KiB
LLVM
95 lines
3.1 KiB
LLVM
; RUN: llc < %s -march=mips -relocation-model=static | \
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; RUN: FileCheck %s -check-prefix=STATIC-O32
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; RUN: llc < %s -march=mips -relocation-model=pic | \
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; RUN: FileCheck %s -check-prefix=PIC-O32
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; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips4 | \
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; RUN: FileCheck %s -check-prefix=PIC-N64
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; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips4 | \
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; RUN: FileCheck %s -check-prefix=STATIC-N64
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; RUN: llc < %s -march=mips64 -relocation-model=pic -mcpu=mips64 | \
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; RUN: FileCheck %s -check-prefix=PIC-N64
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; RUN: llc < %s -march=mips64 -relocation-model=static -mcpu=mips64 | \
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; RUN: FileCheck %s -check-prefix=STATIC-N64
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define i32 @main() nounwind readnone {
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entry:
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%x = alloca i32, align 4 ; <i32*> [#uses=2]
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store volatile i32 2, i32* %x, align 4
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%0 = load volatile i32, i32* %x, align 4 ; <i32> [#uses=1]
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; STATIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
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; STATIC-O32: lui $[[R1:[0-9]+]], %hi($JTI0_0)
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; STATIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; STATIC-O32: lw $[[R3:[0-9]+]], %lo($JTI0_0)($[[R2]])
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; PIC-O32: sll $[[R0:[0-9]+]], ${{[0-9]+}}, 2
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; PIC-O32: lw $[[R1:[0-9]+]], %got($JTI0_0)
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; PIC-O32: addu $[[R2:[0-9]+]], $[[R0]], $[[R1]]
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; PIC-O32: lw $[[R4:[0-9]+]], %lo($JTI0_0)($[[R2]])
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; PIC-O32: addu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
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; PIC-O32: jr $[[R5]]
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; STATIC-N64: dsrl $[[I32:[0-9]]], ${{[0-9]+}}, 32
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; STATIC-N64: dsll $[[R0:[0-9]]], $[[I32]], 3
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; STATIC-N64: lui $[[R1:[0-9]]], %highest(.LJTI0_0)
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; STATIC-N64: daddiu $[[R2:[0-9]]], $[[R1]], %higher(.LJTI0_0)
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; STATIC-N64: dsll $[[R3:[0-9]]], $[[R2]], 16
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; STATIC-N64: daddiu $[[R4:[0-9]]], $[[R3]], %hi(.LJTI0_0)
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; STATIC-N64: dsll $[[R5:[0-9]]], $[[R4]], 16
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; STATIC-N64: daddu $[[R6:[0-9]]], $[[R0]], $[[R4]]
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; STATIC-N64: ld ${{[0-9]+}}, %lo(.LJTI0_0)($[[R6]])
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; PIC-N64: dsll $[[R0:[0-9]+]], ${{[0-9]+}}, 32
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; PIC-N64: ld $[[R1:[0-9]+]], %got_page(.LJTI0_0)
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; PIC-N64: daddu $[[R2:[0-9]+]], $[[R0:[0-9]+]], $[[R1]]
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; PIC-N64: ld $[[R4:[0-9]+]], %got_ofst(.LJTI0_0)($[[R2]])
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; PIC-N64: daddu $[[R5:[0-9]+]], $[[R4:[0-9]+]]
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; PIC-N64: jr $[[R5]]
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switch i32 %0, label %bb4 [
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i32 0, label %bb5
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i32 1, label %bb1
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i32 2, label %bb2
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i32 3, label %bb3
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]
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bb1: ; preds = %entry
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ret i32 2
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bb2: ; preds = %entry
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ret i32 0
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bb3: ; preds = %entry
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ret i32 3
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bb4: ; preds = %entry
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ret i32 4
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bb5: ; preds = %entry
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ret i32 1
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}
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; STATIC-O32: .p2align 2
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; STATIC-O32: $JTI0_0:
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; STATIC-O32: .4byte
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; PIC-O32: .p2align 2
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; PIC-O32: $JTI0_0:
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; PIC-O32: .gpword
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; STATIC-N64: .p2align 3
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; STATIC-N64: LJTI0_0:
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; STATIC-N64: .8byte
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; STATIC-N64: .8byte
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; STATIC-N64: .8byte
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; STATIC-N64: .8byte
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;; PIC-N64: .p2align 3
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; PIC-N64: .LJTI0_0:
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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; PIC-N64: .gpdword
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