Evan Cheng a377b2bbd1 Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode. ... Before: _main: subq $8, %rsp leaq _X(%rip), %rax movsd 8(%rax), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Now: _main: subq $8, %rsp movsd _X+8(%rip), %xmm1 movss _X(%rip), %xmm0 call _t xorl %ecx, %ecx movl %ecx, %eax addq $8, %rsp ret Notice there is another idiotic codegen issue that needs to be fixed asap: xorl %ecx, %ecx movl %ecx, %eax llvm-svn: 46850		2008-02-07 08:53:49 +00:00
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Alpha
ARM	It's PR1925, not PR1609.	2008-02-06 22:07:17 +00:00
CBackend	CBackend: Implement unaligned load/store.	2008-02-01 21:25:59 +00:00
CellSPU	Overhaul Cell SPU's addressing mode internals so that there are now	2008-01-29 02:16:57 +00:00
Generic	Crashes LegalizeTypes with "Do not know how to	2008-02-04 18:07:02 +00:00
IA64
PowerPC	If a vr is already marked alive in a bb, then it has PHI uses that are visited earlier, then it is not killed in the def block (i.e. not dead).	2008-02-05 20:04:18 +00:00
SPARC
X86	Fix a x86-64 codegen deficiency. Allow gv + offset when using rip addressing mode.	2008-02-07 08:53:49 +00:00