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https://github.com/RPCS3/llvm-mirror.git
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2e7bb6da4c
- Allow i16, i32, i64, float, and double types, using the native .u16, .u32, .u64, .f32, and .f64 PTX types. - Allow loading/storing of all primitive types. - Allow primitive types to be passed as parameters. - Allow selection of PTX Version and Shader Model as sub-target attributes. - Merge integer/floating-point test cases for load/store. - Use .u32 instead of .s32 to conform to output from NVidia nvcc compiler. Patch by Justin Holewinski llvm-svn: 126824
272 lines
8.2 KiB
TableGen
272 lines
8.2 KiB
TableGen
//===- PTXRegisterInfo.td - PTX Register defs ----------------*- tblgen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//===----------------------------------------------------------------------===//
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// Declarations that describe the PTX register file
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//===----------------------------------------------------------------------===//
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class PTXReg<string n> : Register<n> {
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let Namespace = "PTX";
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}
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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///===- Predicate Registers -----------------------------------------------===//
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def P0 : PTXReg<"p0">;
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def P1 : PTXReg<"p1">;
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def P2 : PTXReg<"p2">;
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def P3 : PTXReg<"p3">;
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def P4 : PTXReg<"p4">;
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def P5 : PTXReg<"p5">;
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def P6 : PTXReg<"p6">;
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def P7 : PTXReg<"p7">;
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def P8 : PTXReg<"p8">;
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def P9 : PTXReg<"p9">;
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def P10 : PTXReg<"p10">;
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def P11 : PTXReg<"p11">;
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def P12 : PTXReg<"p12">;
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def P13 : PTXReg<"p13">;
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def P14 : PTXReg<"p14">;
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def P15 : PTXReg<"p15">;
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def P16 : PTXReg<"p16">;
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def P17 : PTXReg<"p17">;
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def P18 : PTXReg<"p18">;
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def P19 : PTXReg<"p19">;
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def P20 : PTXReg<"p20">;
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def P21 : PTXReg<"p21">;
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def P22 : PTXReg<"p22">;
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def P23 : PTXReg<"p23">;
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def P24 : PTXReg<"p24">;
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def P25 : PTXReg<"p25">;
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def P26 : PTXReg<"p26">;
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def P27 : PTXReg<"p27">;
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def P28 : PTXReg<"p28">;
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def P29 : PTXReg<"p29">;
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def P30 : PTXReg<"p30">;
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def P31 : PTXReg<"p31">;
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///===- 16-bit Integer Registers ------------------------------------------===//
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def RH0 : PTXReg<"rh0">;
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def RH1 : PTXReg<"rh1">;
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def RH2 : PTXReg<"rh2">;
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def RH3 : PTXReg<"rh3">;
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def RH4 : PTXReg<"rh4">;
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def RH5 : PTXReg<"rh5">;
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def RH6 : PTXReg<"rh6">;
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def RH7 : PTXReg<"rh7">;
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def RH8 : PTXReg<"rh8">;
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def RH9 : PTXReg<"rh9">;
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def RH10 : PTXReg<"rh10">;
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def RH11 : PTXReg<"rh11">;
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def RH12 : PTXReg<"rh12">;
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def RH13 : PTXReg<"rh13">;
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def RH14 : PTXReg<"rh14">;
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def RH15 : PTXReg<"rh15">;
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def RH16 : PTXReg<"rh16">;
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def RH17 : PTXReg<"rh17">;
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def RH18 : PTXReg<"rh18">;
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def RH19 : PTXReg<"rh19">;
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def RH20 : PTXReg<"rh20">;
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def RH21 : PTXReg<"rh21">;
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def RH22 : PTXReg<"rh22">;
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def RH23 : PTXReg<"rh23">;
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def RH24 : PTXReg<"rh24">;
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def RH25 : PTXReg<"rh25">;
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def RH26 : PTXReg<"rh26">;
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def RH27 : PTXReg<"rh27">;
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def RH28 : PTXReg<"rh28">;
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def RH29 : PTXReg<"rh29">;
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def RH30 : PTXReg<"rh30">;
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def RH31 : PTXReg<"rh31">;
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///===- 32-bit Integer Registers ------------------------------------------===//
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def R0 : PTXReg<"r0">;
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def R1 : PTXReg<"r1">;
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def R2 : PTXReg<"r2">;
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def R3 : PTXReg<"r3">;
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def R4 : PTXReg<"r4">;
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def R5 : PTXReg<"r5">;
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def R6 : PTXReg<"r6">;
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def R7 : PTXReg<"r7">;
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def R8 : PTXReg<"r8">;
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def R9 : PTXReg<"r9">;
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def R10 : PTXReg<"r10">;
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def R11 : PTXReg<"r11">;
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def R12 : PTXReg<"r12">;
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def R13 : PTXReg<"r13">;
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def R14 : PTXReg<"r14">;
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def R15 : PTXReg<"r15">;
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def R16 : PTXReg<"r16">;
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def R17 : PTXReg<"r17">;
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def R18 : PTXReg<"r18">;
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def R19 : PTXReg<"r19">;
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def R20 : PTXReg<"r20">;
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def R21 : PTXReg<"r21">;
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def R22 : PTXReg<"r22">;
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def R23 : PTXReg<"r23">;
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def R24 : PTXReg<"r24">;
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def R25 : PTXReg<"r25">;
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def R26 : PTXReg<"r26">;
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def R27 : PTXReg<"r27">;
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def R28 : PTXReg<"r28">;
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def R29 : PTXReg<"r29">;
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def R30 : PTXReg<"r30">;
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def R31 : PTXReg<"r31">;
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///===- 64-bit Integer Registers ------------------------------------------===//
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def RD0 : PTXReg<"rd0">;
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def RD1 : PTXReg<"rd1">;
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def RD2 : PTXReg<"rd2">;
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def RD3 : PTXReg<"rd3">;
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def RD4 : PTXReg<"rd4">;
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def RD5 : PTXReg<"rd5">;
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def RD6 : PTXReg<"rd6">;
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def RD7 : PTXReg<"rd7">;
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def RD8 : PTXReg<"rd8">;
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def RD9 : PTXReg<"rd9">;
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def RD10 : PTXReg<"rd10">;
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def RD11 : PTXReg<"rd11">;
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def RD12 : PTXReg<"rd12">;
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def RD13 : PTXReg<"rd13">;
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def RD14 : PTXReg<"rd14">;
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def RD15 : PTXReg<"rd15">;
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def RD16 : PTXReg<"rd16">;
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def RD17 : PTXReg<"rd17">;
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def RD18 : PTXReg<"rd18">;
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def RD19 : PTXReg<"rd19">;
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def RD20 : PTXReg<"rd20">;
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def RD21 : PTXReg<"rd21">;
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def RD22 : PTXReg<"rd22">;
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def RD23 : PTXReg<"rd23">;
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def RD24 : PTXReg<"rd24">;
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def RD25 : PTXReg<"rd25">;
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def RD26 : PTXReg<"rd26">;
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def RD27 : PTXReg<"rd27">;
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def RD28 : PTXReg<"rd28">;
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def RD29 : PTXReg<"rd29">;
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def RD30 : PTXReg<"rd30">;
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def RD31 : PTXReg<"rd31">;
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///===- 32-bit Floating-Point Registers -----------------------------------===//
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def F0 : PTXReg<"f0">;
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def F1 : PTXReg<"f1">;
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def F2 : PTXReg<"f2">;
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def F3 : PTXReg<"f3">;
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def F4 : PTXReg<"f4">;
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def F5 : PTXReg<"f5">;
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def F6 : PTXReg<"f6">;
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def F7 : PTXReg<"f7">;
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def F8 : PTXReg<"f8">;
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def F9 : PTXReg<"f9">;
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def F10 : PTXReg<"f10">;
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def F11 : PTXReg<"f11">;
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def F12 : PTXReg<"f12">;
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def F13 : PTXReg<"f13">;
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def F14 : PTXReg<"f14">;
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def F15 : PTXReg<"f15">;
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def F16 : PTXReg<"f16">;
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def F17 : PTXReg<"f17">;
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def F18 : PTXReg<"f18">;
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def F19 : PTXReg<"f19">;
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def F20 : PTXReg<"f20">;
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def F21 : PTXReg<"f21">;
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def F22 : PTXReg<"f22">;
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def F23 : PTXReg<"f23">;
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def F24 : PTXReg<"f24">;
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def F25 : PTXReg<"f25">;
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def F26 : PTXReg<"f26">;
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def F27 : PTXReg<"f27">;
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def F28 : PTXReg<"f28">;
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def F29 : PTXReg<"f29">;
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def F30 : PTXReg<"f30">;
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def F31 : PTXReg<"f31">;
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///===- 64-bit Floating-Point Registers -----------------------------------===//
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def FD0 : PTXReg<"fd0">;
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def FD1 : PTXReg<"fd1">;
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def FD2 : PTXReg<"fd2">;
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def FD3 : PTXReg<"fd3">;
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def FD4 : PTXReg<"fd4">;
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def FD5 : PTXReg<"fd5">;
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def FD6 : PTXReg<"fd6">;
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def FD7 : PTXReg<"fd7">;
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def FD8 : PTXReg<"fd8">;
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def FD9 : PTXReg<"fd9">;
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def FD10 : PTXReg<"fd10">;
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def FD11 : PTXReg<"fd11">;
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def FD12 : PTXReg<"fd12">;
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def FD13 : PTXReg<"fd13">;
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def FD14 : PTXReg<"fd14">;
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def FD15 : PTXReg<"fd15">;
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def FD16 : PTXReg<"fd16">;
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def FD17 : PTXReg<"fd17">;
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def FD18 : PTXReg<"fd18">;
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def FD19 : PTXReg<"fd19">;
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def FD20 : PTXReg<"fd20">;
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def FD21 : PTXReg<"fd21">;
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def FD22 : PTXReg<"fd22">;
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def FD23 : PTXReg<"fd23">;
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def FD24 : PTXReg<"fd24">;
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def FD25 : PTXReg<"fd25">;
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def FD26 : PTXReg<"fd26">;
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def FD27 : PTXReg<"fd27">;
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def FD28 : PTXReg<"fd28">;
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def FD29 : PTXReg<"fd29">;
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def FD30 : PTXReg<"fd30">;
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def FD31 : PTXReg<"fd31">;
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Preds : RegisterClass<"PTX", [i1], 8,
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[P0, P1, P2, P3, P4, P5, P6, P7,
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P8, P9, P10, P11, P12, P13, P14, P15,
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P16, P17, P18, P19, P20, P21, P22, P23,
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P24, P25, P26, P27, P28, P29, P30, P31]>;
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def RRegu16 : RegisterClass<"PTX", [i16], 16,
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[RH0, RH1, RH2, RH3, RH4, RH5, RH6, RH7,
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RH8, RH9, RH10, RH11, RH12, RH13, RH14, RH15,
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RH16, RH17, RH18, RH19, RH20, RH21, RH22, RH23,
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RH24, RH25, RH26, RH27, RH28, RH29, RH30, RH31]>;
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def RRegu32 : RegisterClass<"PTX", [i32], 32,
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[R0, R1, R2, R3, R4, R5, R6, R7,
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R8, R9, R10, R11, R12, R13, R14, R15,
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R16, R17, R18, R19, R20, R21, R22, R23,
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R24, R25, R26, R27, R28, R29, R30, R31]>;
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def RRegu64 : RegisterClass<"PTX", [i64], 64,
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[RD0, RD1, RD2, RD3, RD4, RD5, RD6, RD7,
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RD8, RD9, RD10, RD11, RD12, RD13, RD14, RD15,
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RD16, RD17, RD18, RD19, RD20, RD21, RD22, RD23,
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RD24, RD25, RD26, RD27, RD28, RD29, RD30, RD31]>;
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def RRegf32 : RegisterClass<"PTX", [f32], 32,
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[F0, F1, F2, F3, F4, F5, F6, F7,
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F8, F9, F10, F11, F12, F13, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23,
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F24, F25, F26, F27, F28, F29, F30, F31]>;
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def RRegf64 : RegisterClass<"PTX", [f64], 64,
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[FD0, FD1, FD2, FD3, FD4, FD5, FD6, FD7,
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FD8, FD9, FD10, FD11, FD12, FD13, FD14, FD15,
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FD16, FD17, FD18, FD19, FD20, FD21, FD22, FD23,
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FD24, FD25, FD26, FD27, FD28, FD29, FD30, FD31]>;
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