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e24daf0c1e
This patch allows target shuffles to be combined to single input immediate permute instructions - (V)PSHUFD/VPERMILPD/VPERMILPS - allowing more general pattern matching than what we current do and improves the likelihood of memory folding compared to existing patterns which tend to reuse the input in multiple arguments. Further permute instructions (V)PSHUFLW/(V)PSHUFHW/(V)PERMQ/(V)PERMPD may be added in the future but its proven tricky to create tests cases for them so far. (V)PSHUFLW/(V)PSHUFHW is already handled quite well in combineTargetShuffle so it may be that removing some of that code may allow us to perform more of the combining in one place without duplication. Differential Revision: http://reviews.llvm.org/D21148 llvm-svn: 273999
91 lines
3.7 KiB
LLVM
91 lines
3.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown -mattr=+ssse3 | FileCheck %s
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; Test that the pshufb mask comment is correct.
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define <16 x i8> @test1(<16 x i8> %V) {
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; CHECK-LABEL: test1:
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; CHECK: # BB#0:
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; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,0,0,0,0,2,0,0,0,0,3,0,0,0,0,4]
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; CHECK-NEXT: retq
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%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8 0, i8 0, i8 2, i8 0, i8 0, i8 0, i8 0, i8 3, i8 0, i8 0, i8 0, i8 0, i8 4>)
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ret <16 x i8> %1
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}
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; Test that indexes larger than the size of the vector are shown masked (bottom 4 bits).
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define <16 x i8> @test2(<16 x i8> %V) {
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; CHECK-LABEL: test2:
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; CHECK: # BB#0:
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; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[15,0,0,0,0,0,0,0,0,0,1,0,0,0,0,2]
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; CHECK-NEXT: retq
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%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 15, i8 0, i8 0, i8 0, i8 0, i8 16, i8 0, i8 0, i8 0, i8 0, i8 17, i8 0, i8 0, i8 0, i8 0, i8 50>)
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ret <16 x i8> %1
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}
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; Test that indexes with bit seven set are shown as zero.
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define <16 x i8> @test3(<16 x i8> %V) {
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; CHECK-LABEL: test3:
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; CHECK: # BB#0:
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; CHECK-NEXT: pshufb {{.*#+}} xmm0 = xmm0[1,0,0,15,0,2,0,0],zero,xmm0[0,3,0,0],zero,xmm0[0,4]
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; CHECK-NEXT: retq
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%1 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> <i8 1, i8 0, i8 0, i8 127, i8 0, i8 2, i8 0, i8 0, i8 128, i8 0, i8 3, i8 0, i8 0, i8 255, i8 0, i8 4>)
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ret <16 x i8> %1
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}
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; Test that we won't crash when the constant was reused for another instruction.
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define <16 x i8> @test4(<16 x i8> %V, <2 x i64>* %P) {
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; CHECK-LABEL: test4:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [1084818905618843912,506097522914230528]
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; CHECK-NEXT: movaps %xmm1, (%rdi)
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; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1]
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; CHECK-NEXT: retq
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%1 = insertelement <2 x i64> undef, i64 1084818905618843912, i32 0
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%2 = insertelement <2 x i64> %1, i64 506097522914230528, i32 1
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store <2 x i64> %2, <2 x i64>* %P, align 16
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%3 = bitcast <2 x i64> %2 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %3)
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ret <16 x i8> %4
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}
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define <16 x i8> @test5(<16 x i8> %V) {
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; CHECK-LABEL: test5:
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; CHECK: # BB#0:
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; CHECK-NEXT: movl $1, %eax
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; CHECK-NEXT: movd %rax, %xmm1
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; CHECK-NEXT: movaps %xmm1, (%rax)
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; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1]
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; CHECK-NEXT: movdqa %xmm1, (%rax)
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; CHECK-NEXT: pshufb %xmm1, %xmm0
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; CHECK-NEXT: retq
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store <2 x i64> <i64 1, i64 0>, <2 x i64>* undef, align 16
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%l = load <2 x i64>, <2 x i64>* undef, align 16
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%shuffle = shufflevector <2 x i64> %l, <2 x i64> undef, <2 x i32> zeroinitializer
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store <2 x i64> %shuffle, <2 x i64>* undef, align 16
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%1 = load <16 x i8>, <16 x i8>* undef, align 16
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%2 = call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %1)
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ret <16 x i8> %2
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}
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; Test for a reused constant that would allow the pshufb to combine to a simpler instruction.
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define <16 x i8> @test6(<16 x i8> %V, <2 x i64>* %P) {
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; CHECK-LABEL: test6:
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; CHECK: # BB#0:
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; CHECK-NEXT: movaps {{.*#+}} xmm1 = [217019414673948672,506380106026255364]
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; CHECK-NEXT: movaps %xmm1, (%rdi)
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; CHECK-NEXT: punpcklbw {{.*#+}} xmm0 = xmm0[0,0,1,1,2,2,3,3,4,4,5,5,6,6,7,7]
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; CHECK-NEXT: retq
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%1 = insertelement <2 x i64> undef, i64 217019414673948672, i32 0
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%2 = insertelement <2 x i64> %1, i64 506380106026255364, i32 1
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store <2 x i64> %2, <2 x i64>* %P, align 16
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%3 = bitcast <2 x i64> %2 to <16 x i8>
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%4 = tail call <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8> %V, <16 x i8> %3)
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ret <16 x i8> %4
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}
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declare <16 x i8> @llvm.x86.ssse3.pshuf.b.128(<16 x i8>, <16 x i8>) nounwind readnone
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