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40 lines
2.0 KiB
LLVM
40 lines
2.0 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=FUNC -check-prefix=SI %s
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; FUNC-LABEL: {{^}}fmul_f64:
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmul_f64(double addrspace(1)* %out, double addrspace(1)* %in1,
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double addrspace(1)* %in2) {
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%r0 = load double, double addrspace(1)* %in1
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%r1 = load double, double addrspace(1)* %in2
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%r2 = fmul double %r0, %r1
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store double %r2, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fmul_v2f64:
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmul_v2f64(<2 x double> addrspace(1)* %out, <2 x double> addrspace(1)* %in1,
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<2 x double> addrspace(1)* %in2) {
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%r0 = load <2 x double>, <2 x double> addrspace(1)* %in1
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%r1 = load <2 x double>, <2 x double> addrspace(1)* %in2
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%r2 = fmul <2 x double> %r0, %r1
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store <2 x double> %r2, <2 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fmul_v4f64:
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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; SI: v_mul_f64 {{v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\], v\[[0-9]+:[0-9]+\]}}
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define amdgpu_kernel void @fmul_v4f64(<4 x double> addrspace(1)* %out, <4 x double> addrspace(1)* %in1,
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<4 x double> addrspace(1)* %in2) {
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%r0 = load <4 x double>, <4 x double> addrspace(1)* %in1
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%r1 = load <4 x double>, <4 x double> addrspace(1)* %in2
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%r2 = fmul <4 x double> %r0, %r1
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store <4 x double> %r2, <4 x double> addrspace(1)* %out
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ret void
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}
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