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2e752c587f
Since v_max_f32_e64/v_max_f16_e64 can be folded if the target
instruction supports the clamp bit, we also need to maintain
modifiers when converting v_mac to v_mad.
This fixes a rendering issue with Dirt Rally because a v_mac
instruction with the clamp bit set was converted to a v_mad
but that bit was lost during the conversion.
Fixes: e184e01dd79 ("AMDGPU: Fold FP clamp as modifier bit")
Patch by Samuel Pitoiset <samuel.pitoiset@gmail.com>
llvm-svn: 297556
298 lines
11 KiB
LLVM
298 lines
11 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -check-prefix=VI %s
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; IEEE bit enabled for compute kernel, no shouldn't use.
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; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_signed_zeros:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(float addrspace(1)* %out, float addrspace(1)* %aptr) #4 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, float addrspace(1)* %out.gep
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ret void
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}
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; IEEE bit enabled for compute kernel, no shouldn't use even though nsz is allowed
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; GCN-LABEL: {{^}}v_omod_div2_f32_enable_ieee_nsz:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, [[A]]{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_nsz(float addrspace(1)* %out, float addrspace(1)* %aptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep0 = getelementptr float, float addrspace(1)* %aptr, i32 %tid
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%out.gep = getelementptr float, float addrspace(1)* %out, i32 %tid
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%a = load float, float addrspace(1)* %gep0
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, float addrspace(1)* %out.gep
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ret void
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}
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; Only allow without IEEE bit if signed zeros are significant.
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; GCN-LABEL: {{^}}v_omod_div2_f32_signed_zeros:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_div2_f32_signed_zeros(float %a) #4 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_div2_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 div:2{{$}}
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define amdgpu_ps void @v_omod_div2_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_mul2_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:2{{$}}
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define amdgpu_ps void @v_omod_mul2_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 2.0
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_mul4_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:4{{$}}
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define amdgpu_ps void @v_omod_mul4_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 4.0
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_mul4_multi_use_f32:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 4.0, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_mul4_multi_use_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 4.0
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store float %div2, float addrspace(1)* undef
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store volatile float %add, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_mul4_dbg_use_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 mul:4{{$}}
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define amdgpu_ps void @v_omod_mul4_dbg_use_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10
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%div2 = fmul float %add, 4.0
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; Clamp is applied after omod, folding both into instruction is OK.
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; GCN-LABEL: {{^}}v_clamp_omod_div2_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, 1.0 clamp div:2{{$}}
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define amdgpu_ps void @v_clamp_omod_div2_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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%max = call float @llvm.maxnum.f32(float %div2, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* undef
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ret void
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}
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; Cannot fold omod into clamp
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; GCN-LABEL: {{^}}v_omod_div2_clamp_f32:
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; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], v0, 1.0 clamp{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_div2_clamp_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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%div2 = fmul float %clamp, 0.5
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_div2_abs_src_f32:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; GCN: v_mul_f32_e64 v{{[0-9]+}}, |[[ADD]]|, 0.5{{$}}
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define amdgpu_ps void @v_omod_div2_abs_src_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%abs.add = call float @llvm.fabs.f32(float %add)
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%div2 = fmul float %abs.add, 0.5
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_add_self_clamp_f32:
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; GCN: v_add_f32_e64 v{{[0-9]+}}, v0, v0 clamp{{$}}
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define amdgpu_ps void @v_omod_add_self_clamp_f32(float %a) #0 {
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%add = fadd float %a, %a
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%max = call float @llvm.maxnum.f32(float %add, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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store float %clamp, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_add_clamp_self_f32:
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; GCN: v_max_f32_e64 [[CLAMP:v[0-9]+]], v0, v0 clamp{{$}}
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; GCN: v_add_f32_e32 v{{[0-9]+}}, [[CLAMP]], [[CLAMP]]{{$}}
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define amdgpu_ps void @v_omod_add_clamp_self_f32(float %a) #0 {
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%max = call float @llvm.maxnum.f32(float %a, float 0.0)
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%clamp = call float @llvm.minnum.f32(float %max, float 1.0)
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%add = fadd float %clamp, %clamp
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store float %add, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_add_abs_self_f32:
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; GCN: v_add_f32_e32 [[X:v[0-9]+]], 1.0, v0
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; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, |[[X]]|{{$}}
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define amdgpu_ps void @v_omod_add_abs_self_f32(float %a) #0 {
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%x = fadd float %a, 1.0
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%abs.x = call float @llvm.fabs.f32(float %x)
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%add = fadd float %abs.x, %abs.x
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store float %add, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_add_abs_x_x_f32:
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; GCN: v_add_f32_e32 [[X:v[0-9]+]], 1.0, v0
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; GCN: v_add_f32_e64 v{{[0-9]+}}, |[[X]]|, [[X]]{{$}}
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define amdgpu_ps void @v_omod_add_abs_x_x_f32(float %a) #0 {
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%x = fadd float %a, 1.0
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%abs.x = call float @llvm.fabs.f32(float %x)
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%add = fadd float %abs.x, %x
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store float %add, float addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_add_x_abs_x_f32:
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; GCN: v_add_f32_e32 [[X:v[0-9]+]], 1.0, v0
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; GCN: v_add_f32_e64 v{{[0-9]+}}, [[X]], |[[X]]|{{$}}
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define amdgpu_ps void @v_omod_add_x_abs_x_f32(float %a) #0 {
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%x = fadd float %a, 1.0
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%abs.x = call float @llvm.fabs.f32(float %x)
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%add = fadd float %x, %abs.x
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store float %add, float addrspace(1)* undef
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ret void
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}
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; Don't fold omod into omod into another omod.
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; GCN-LABEL: {{^}}v_omod_div2_omod_div2_f32:
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; GCN: v_add_f32_e64 [[ADD:v[0-9]+]], v0, 1.0 div:2{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_div2_omod_div2_f32(float %a) #0 {
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%add = fadd float %a, 1.0
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%div2.0 = fmul float %add, 0.5
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%div2.1 = fmul float %div2.0, 0.5
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store float %div2.1, float addrspace(1)* undef
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ret void
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}
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; Don't fold omod if denorms enabled
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; GCN-LABEL: {{^}}v_omod_div2_f32_denormals:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; GCN: v_mul_f32_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_div2_f32_denormals(float %a) #2 {
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%add = fadd float %a, 1.0
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%div2 = fmul float %add, 0.5
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store float %div2, float addrspace(1)* undef
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ret void
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}
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; Don't fold omod if denorms enabled for add form.
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; GCN-LABEL: {{^}}v_omod_mul2_f32_denormals:
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; GCN: v_add_f32_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; GCN: v_add_f32_e32 v{{[0-9]+}}, [[ADD]], [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_mul2_f32_denormals(float %a) #2 {
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%add = fadd float %a, 1.0
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%mul2 = fadd float %add, %add
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store float %mul2, float addrspace(1)* undef
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ret void
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}
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; Don't fold omod if denorms enabled
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; GCN-LABEL: {{^}}v_omod_div2_f16_denormals:
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; VI: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; VI: v_mul_f16_e32 v{{[0-9]+}}, 0.5, [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {
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%add = fadd half %a, 1.0
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%div2 = fmul half %add, 0.5
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store half %div2, half addrspace(1)* undef
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ret void
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}
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; Don't fold omod if denorms enabled for add form.
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; GCN-LABEL: {{^}}v_omod_mul2_f16_denormals:
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; VI: v_add_f16_e32 [[ADD:v[0-9]+]], 1.0, v0{{$}}
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; VI: v_add_f16_e32 v{{[0-9]+}}, [[ADD]], [[ADD]]{{$}}
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define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {
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%add = fadd half %a, 1.0
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%mul2 = fadd half %add, %add
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store half %mul2, half addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_div2_f16_no_denormals:
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; VI-NOT: v0
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; VI: v_add_f16_e64 [[ADD:v[0-9]+]], v0, 1.0 div:2{{$}}
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define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {
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%add = fadd half %a, 1.0
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%div2 = fmul half %add, 0.5
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store half %div2, half addrspace(1)* undef
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ret void
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}
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; GCN-LABEL: {{^}}v_omod_mac_to_mad:
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; GCN: v_mad_f32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]}} mul:2{{$}}
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define amdgpu_ps void @v_omod_mac_to_mad(float %b, float %a) #0 {
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%mul = fmul float %a, %a
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%add = fadd float %mul, %b
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%mad = fmul float %add, 2.0
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%res = fmul float %mad, %b
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store float %res, float addrspace(1)* undef
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.fabs.f32(float) #1
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declare float @llvm.floor.f32(float) #1
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declare float @llvm.minnum.f32(float, float) #1
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declare float @llvm.maxnum.f32(float, float) #1
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declare float @llvm.amdgcn.fmed3.f32(float, float, float) #1
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declare double @llvm.fabs.f64(double) #1
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declare double @llvm.minnum.f64(double, double) #1
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declare double @llvm.maxnum.f64(double, double) #1
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declare half @llvm.fabs.f16(half) #1
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declare half @llvm.minnum.f16(half, half) #1
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declare half @llvm.maxnum.f16(half, half) #1
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1
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attributes #0 = { nounwind "no-signed-zeros-fp-math"="true" }
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attributes #1 = { nounwind readnone }
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attributes #2 = { nounwind "target-features"="+fp32-denormals" "no-signed-zeros-fp-math"="true" }
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attributes #3 = { nounwind "target-features"="-fp64-fp16-denormals" "no-signed-zeros-fp-math"="true" }
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attributes #4 = { nounwind "no-signed-zeros-fp-math"="false" }
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!llvm.dbg.cu = !{!0}
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!llvm.module.flags = !{!2, !3}
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!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug)
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!1 = !DIFile(filename: "/tmp/foo.cl", directory: "/dev/null")
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!2 = !{i32 2, !"Dwarf Version", i32 4}
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!3 = !{i32 2, !"Debug Info Version", i32 3}
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!4 = !DILocalVariable(name: "add", arg: 1, scope: !5, file: !1, line: 1)
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!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)
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!6 = !DISubroutineType(types: !7)
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!7 = !{null, !8}
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!8 = !DIBasicType(name: "float", size: 32, align: 32)
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!9 = !DIExpression()
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!10 = !DILocation(line: 1, column: 42, scope: !5)
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