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2b0231f519
This replaces most argument uses with loads, but for now not all. The code in SelectionDAG for calling convention lowering is actively harmful for amdgpu_kernel. It attempts to split the argument types into register legal types, which results in low quality code for arbitary types. Since all kernel arguments are passed in memory, we just want the raw types. I've tried a couple of methods of mitigating this in SelectionDAG, but it's easier to just bypass this problem alltogether. It's possible to hack around the problem in the initial lowering, but the real problem is the DAG then expects to be able to use CopyToReg/CopyFromReg for uses of the arguments outside the block. Exposing the argument loads in the IR also has the advantage that the LoadStoreVectorizer can merge them. I'm not sure the best approach to dealing with the IR argument list is. The patch as-is just leaves the IR arguments in place, so all the existing code will still compute the same kernarg size and pointlessly lowers the arguments. Arguably the frontend should emit kernels with an empty argument list in the first place. Alternatively a dummy array could be inserted as a single argument just to reserve space. This does have some disadvantages. Local pointer kernel arguments can no longer have AssertZext placed on them as the equivalent !range metadata is not valid on pointer typed loads. This is mostly bad for SI which needs to know about the known bits in order to use the DS instruction offset, so in this case this is not done. More importantly, this skips noalias arguments since this pass does not yet convert this to the equivalent !alias.scope and !noalias metadata. Producing this metadata correctly seems to be tricky, although this logically is the same as inlining into a function which doesn't exist. Additionally, exposing these loads to the vectorizer may result in degraded aliasing information if a pointer load is merged with another argument load. I'm also not entirely sure this is preserving the current clover ABI, although I would greatly prefer if it would stop widening arguments and match the HSA ABI. As-is I think it is extending < 4-byte arguments to 4-bytes but doesn't align them to 4-bytes. llvm-svn: 335650
126 lines
5.1 KiB
LLVM
126 lines
5.1 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=SI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN -check-prefix=VI %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress < %s | FileCheck -enable-var-scope -check-prefix=EG %s
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declare i32 @llvm.r600.read.tidig.x() nounwind readnone
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define amdgpu_kernel void @trunc_i64_to_i32_store(i32 addrspace(1)* %out, [8 x i32], i64 %in) {
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; GCN-LABEL: {{^}}trunc_i64_to_i32_store:
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; GCN: s_load_dword [[SLOAD:s[0-9]+]], s[0:1],
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; GCN: v_mov_b32_e32 [[VLOAD:v[0-9]+]], [[SLOAD]]
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; SI: buffer_store_dword [[VLOAD]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VLOAD]]
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; EG-LABEL: {{^}}trunc_i64_to_i32_store:
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; EG: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
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; EG: LSHR
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; EG-NEXT: 2(
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%result = trunc i64 %in to i32 store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_load_shl_i64:
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; GCN-DAG: s_load_dwordx2
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; GCN-DAG: s_load_dword [[SREG:s[0-9]+]],
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; GCN: s_lshl_b32 [[SHL:s[0-9]+]], [[SREG]], 2
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; GCN: v_mov_b32_e32 [[VSHL:v[0-9]+]], [[SHL]]
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; SI: buffer_store_dword [[VSHL]]
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; VI: flat_store_dword v[{{[0-9:]+}}], [[VSHL]]
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define amdgpu_kernel void @trunc_load_shl_i64(i32 addrspace(1)* %out, [8 x i32], i64 %a) {
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%b = shl i64 %a, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_shl_i64:
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; SI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0xd
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; VI: s_load_dwordx2 s{{\[}}[[LO_SREG:[0-9]+]]:{{[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, 0x34
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; GCN: s_lshl_b64 s{{\[}}[[LO_SHL:[0-9]+]]:{{[0-9]+\]}}, s{{\[}}[[LO_SREG]]:{{[0-9]+\]}}, 2
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; GCN: s_add_u32 s[[LO_SREG2:[0-9]+]], s[[LO_SHL]],
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; GCN: v_mov_b32_e32 v[[LO_VREG:[0-9]+]], s[[LO_SREG2]]
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; GCN: s_addc_u32
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; SI: buffer_store_dword v[[LO_VREG]],
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; VI: flat_store_dword v[{{[0-9:]+}}], v[[LO_VREG]]
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; GCN: v_mov_b32_e32
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; GCN: v_mov_b32_e32
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define amdgpu_kernel void @trunc_shl_i64(i64 addrspace(1)* %out2, i32 addrspace(1)* %out, i64 %a) {
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%aa = add i64 %a, 234 ; Prevent shrinking store.
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%b = shl i64 %aa, 2
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%result = trunc i64 %b to i32
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store i32 %result, i32 addrspace(1)* %out, align 4
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store i64 %b, i64 addrspace(1)* %out2, align 8 ; Prevent reducing ops to 32-bits
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i32_to_i1:
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; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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define amdgpu_kernel void @trunc_i32_to_i1(i32 addrspace(1)* %out, i32 addrspace(1)* %ptr) {
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%a = load i32, i32 addrspace(1)* %ptr, align 4
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}trunc_i8_to_i1:
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; GCN: v_and_b32_e32 [[VREG:v[0-9]+]], 1, v{{[0-9]+}}
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define amdgpu_kernel void @trunc_i8_to_i1(i8 addrspace(1)* %out, i8 addrspace(1)* %ptr) {
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%a = load i8, i8 addrspace(1)* %ptr, align 4
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%trunc = trunc i8 %a to i1
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%result = select i1 %trunc, i8 1, i8 0
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store i8 %result, i8 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i16_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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define amdgpu_kernel void @sgpr_trunc_i16_to_i1(i16 addrspace(1)* %out, i16 %a) {
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%trunc = trunc i16 %a to i1
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%result = select i1 %trunc, i16 1, i16 0
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store i16 %result, i16 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}sgpr_trunc_i32_to_i1:
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; GCN: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 1
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define amdgpu_kernel void @sgpr_trunc_i32_to_i1(i32 addrspace(1)* %out, i32 %a) {
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%trunc = trunc i32 %a to i1
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%result = select i1 %trunc, i32 1, i32 0
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store i32 %result, i32 addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}s_trunc_i64_to_i1:
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; SI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x13
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; VI: s_load_dwordx2 s{{\[}}[[SLO:[0-9]+]]:{{[0-9]+\]}}, {{s\[[0-9]+:[0-9]+\]}}, 0x4c
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; GCN: s_and_b32 [[MASKED:s[0-9]+]], 1, s[[SLO]]
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; GCN: v_cmp_eq_u32_e64 s{{\[}}[[VLO:[0-9]+]]:[[VHI:[0-9]+]]], [[MASKED]], 1{{$}}
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, s{{\[}}[[VLO]]:[[VHI]]]
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define amdgpu_kernel void @s_trunc_i64_to_i1(i32 addrspace(1)* %out, [8 x i32], i64 %x) {
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%trunc = trunc i64 %x to i1
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%sel = select i1 %trunc, i32 63, i32 -12
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store i32 %sel, i32 addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}v_trunc_i64_to_i1:
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; SI: buffer_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; VI: flat_load_dwordx2 v{{\[}}[[VLO:[0-9]+]]:{{[0-9]+\]}}
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; GCN: v_and_b32_e32 [[MASKED:v[0-9]+]], 1, v[[VLO]]
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; GCN: v_cmp_eq_u32_e32 vcc, 1, [[MASKED]]
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; GCN: v_cndmask_b32_e64 {{v[0-9]+}}, -12, 63, vcc
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define amdgpu_kernel void @v_trunc_i64_to_i1(i32 addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
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%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%out.gep = getelementptr i32, i32 addrspace(1)* %out, i32 %tid
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%x = load i64, i64 addrspace(1)* %gep
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%trunc = trunc i64 %x to i1
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%sel = select i1 %trunc, i32 63, i32 -12
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store i32 %sel, i32 addrspace(1)* %out.gep
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ret void
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}
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