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https://github.com/RPCS3/llvm-mirror.git
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162 lines
6.5 KiB
LLVM
162 lines
6.5 KiB
LLVM
; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,SI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,VI,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX9,FUNC %s
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; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=cypress -verify-machineinstrs < %s | FileCheck -check-prefixes=EG,FUNC %s
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; FUNC-LABEL: {{^}}s_uaddo_i64_zext:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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; GCN: v_cmp_lt_u64_e32 vcc
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; EG: ADDC_UINT
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; EG: ADDC_UINT
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define amdgpu_kernel void @s_uaddo_i64_zext(i64 addrspace(1)* %out, i64 %a, i64 %b) #0 {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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%ext = zext i1 %carry to i64
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%add2 = add i64 %val, %ext
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store i64 %add2, i64 addrspace(1)* %out, align 8
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ret void
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}
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; FIXME: Could do scalar
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; FUNC-LABEL: {{^}}s_uaddo_i32:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, s{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @s_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 %a, i32 %b) #0 {
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i32:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i32(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep, align 4
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%b = load i32, i32 addrspace(1)* %b.gep, align 4
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store i32 %val, i32 addrspace(1)* %out, align 4
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i32_novcc:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GCN: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i32_novcc(i32 addrspace(1)* %out, i1 addrspace(1)* %carryout, i32 addrspace(1)* %a.ptr, i32 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i32, i32 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i32, i32 addrspace(1)* %b.ptr
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%a = load i32, i32 addrspace(1)* %a.gep, align 4
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%b = load i32, i32 addrspace(1)* %b.gep, align 4
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%uadd = call { i32, i1 } @llvm.uadd.with.overflow.i32(i32 %a, i32 %b)
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%val = extractvalue { i32, i1 } %uadd, 0
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%carry = extractvalue { i32, i1 } %uadd, 1
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store volatile i32 %val, i32 addrspace(1)* %out, align 4
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call void asm sideeffect "", "~{VCC}"() #0
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store volatile i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}s_uaddo_i64:
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; GCN: s_add_u32
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; GCN: s_addc_u32
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @s_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 %a, i64 %b) #0 {
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i64:
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; SI: v_add_i32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; SI: v_addc_u32_e32 v{{[0-9]+}}, vcc,
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; VI: v_add_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; VI: v_addc_u32_e32 v{{[0-9]+}}, vcc,
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; GFX9: v_add_co_u32_e32 v{{[0-9]+}}, vcc, v{{[0-9]+}}, v{{[0-9]+}}
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; GFX9: v_addc_co_u32_e32 v{{[0-9]+}}, vcc,
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; EG: ADDC_UINT
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; EG: ADD_INT
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define amdgpu_kernel void @v_uaddo_i64(i64 addrspace(1)* %out, i1 addrspace(1)* %carryout, i64 addrspace(1)* %a.ptr, i64 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i64, i64 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i64, i64 addrspace(1)* %b.ptr
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%a = load i64, i64 addrspace(1)* %a.gep
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%b = load i64, i64 addrspace(1)* %b.gep
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%uadd = call { i64, i1 } @llvm.uadd.with.overflow.i64(i64 %a, i64 %b)
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%val = extractvalue { i64, i1 } %uadd, 0
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%carry = extractvalue { i64, i1 } %uadd, 1
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store i64 %val, i64 addrspace(1)* %out
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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; FUNC-LABEL: {{^}}v_uaddo_i16:
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; VI: v_add_u16_e32
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; VI: v_cmp_lt_u16_e32
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; GFX9: v_add_u16_e32
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; GFX9: v_cmp_lt_u16_e32
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define amdgpu_kernel void @v_uaddo_i16(i16 addrspace(1)* %out, i1 addrspace(1)* %carryout, i16 addrspace(1)* %a.ptr, i16 addrspace(1)* %b.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds i16, i16 addrspace(1)* %a.ptr
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%b.gep = getelementptr inbounds i16, i16 addrspace(1)* %b.ptr
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%a = load i16, i16 addrspace(1)* %a.gep
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%b = load i16, i16 addrspace(1)* %b.gep
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%uadd = call { i16, i1 } @llvm.uadd.with.overflow.i16(i16 %a, i16 %b)
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%val = extractvalue { i16, i1 } %uadd, 0
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%carry = extractvalue { i16, i1 } %uadd, 1
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store i16 %val, i16 addrspace(1)* %out
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store i1 %carry, i1 addrspace(1)* %carryout
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare { i16, i1 } @llvm.uadd.with.overflow.i16(i16, i16) #1
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declare { i32, i1 } @llvm.uadd.with.overflow.i32(i32, i32) #1
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declare { i64, i1 } @llvm.uadd.with.overflow.i64(i64, i64) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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