mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 03:23:01 +02:00
fad0fd9a71
Summary: LLVM defaults to the newer .init_array/.fini_array scheme for static constructors rather than the less desirable .ctors/.dtors (the UseCtors flag defaults to false). This wasn't being respected in the RISC-V backend because it fails to call TargetLoweringObjectFileELF::InitializeELF with the the appropriate flag for UseInitArray. This patch fixes this by implementing RISCVELFTargetObjectFile and overriding its Initialize method to call InitializeELF(TM.Options.UseInitArray). Reviewers: asb, apazos Reviewed By: asb Subscribers: mgorny, rbar, johnrusso, simoncook, jordy.potman.lists, sabuasal, niosHD, kito-cheng, shiva0217, llvm-commits Differential Revision: https://reviews.llvm.org/D44750 llvm-svn: 328433
94 lines
3.0 KiB
C++
94 lines
3.0 KiB
C++
//===-- RISCVTargetMachine.cpp - Define TargetMachine for RISCV -----------===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// Implements the info about RISCV target spec.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#include "RISCV.h"
|
|
#include "RISCVTargetMachine.h"
|
|
#include "RISCVTargetObjectFile.h"
|
|
#include "llvm/ADT/STLExtras.h"
|
|
#include "llvm/CodeGen/Passes.h"
|
|
#include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
|
|
#include "llvm/CodeGen/TargetPassConfig.h"
|
|
#include "llvm/IR/LegacyPassManager.h"
|
|
#include "llvm/Support/FormattedStream.h"
|
|
#include "llvm/Support/TargetRegistry.h"
|
|
#include "llvm/Target/TargetOptions.h"
|
|
using namespace llvm;
|
|
|
|
extern "C" void LLVMInitializeRISCVTarget() {
|
|
RegisterTargetMachine<RISCVTargetMachine> X(getTheRISCV32Target());
|
|
RegisterTargetMachine<RISCVTargetMachine> Y(getTheRISCV64Target());
|
|
}
|
|
|
|
static std::string computeDataLayout(const Triple &TT) {
|
|
if (TT.isArch64Bit()) {
|
|
return "e-m:e-p:64:64-i64:64-i128:128-n64-S128";
|
|
} else {
|
|
assert(TT.isArch32Bit() && "only RV32 and RV64 are currently supported");
|
|
return "e-m:e-p:32:32-i64:64-n32-S128";
|
|
}
|
|
}
|
|
|
|
static Reloc::Model getEffectiveRelocModel(const Triple &TT,
|
|
Optional<Reloc::Model> RM) {
|
|
if (!RM.hasValue())
|
|
return Reloc::Static;
|
|
return *RM;
|
|
}
|
|
|
|
static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
|
|
if (CM)
|
|
return *CM;
|
|
return CodeModel::Small;
|
|
}
|
|
|
|
RISCVTargetMachine::RISCVTargetMachine(const Target &T, const Triple &TT,
|
|
StringRef CPU, StringRef FS,
|
|
const TargetOptions &Options,
|
|
Optional<Reloc::Model> RM,
|
|
Optional<CodeModel::Model> CM,
|
|
CodeGenOpt::Level OL, bool JIT)
|
|
: LLVMTargetMachine(T, computeDataLayout(TT), TT, CPU, FS, Options,
|
|
getEffectiveRelocModel(TT, RM),
|
|
getEffectiveCodeModel(CM), OL),
|
|
TLOF(make_unique<RISCVELFTargetObjectFile>()),
|
|
Subtarget(TT, CPU, FS, *this) {
|
|
initAsmInfo();
|
|
}
|
|
|
|
namespace {
|
|
class RISCVPassConfig : public TargetPassConfig {
|
|
public:
|
|
RISCVPassConfig(RISCVTargetMachine &TM, PassManagerBase &PM)
|
|
: TargetPassConfig(TM, PM) {}
|
|
|
|
RISCVTargetMachine &getRISCVTargetMachine() const {
|
|
return getTM<RISCVTargetMachine>();
|
|
}
|
|
|
|
bool addInstSelector() override;
|
|
void addPreEmitPass() override;
|
|
};
|
|
}
|
|
|
|
TargetPassConfig *RISCVTargetMachine::createPassConfig(PassManagerBase &PM) {
|
|
return new RISCVPassConfig(*this, PM);
|
|
}
|
|
|
|
bool RISCVPassConfig::addInstSelector() {
|
|
addPass(createRISCVISelDag(getRISCVTargetMachine()));
|
|
|
|
return false;
|
|
}
|
|
|
|
void RISCVPassConfig::addPreEmitPass() { addPass(&BranchRelaxationPassID); }
|