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330821bce0
Fast register pressure tracking currently only takes effect during bottom up scheduling. Forcing this is a bit faster and simpler for targets that don't have many scheduling constraints and don't need top-down scheduling. llvm-svn: 190014
50 lines
1.7 KiB
LLVM
50 lines
1.7 KiB
LLVM
; REQUIRES: asserts
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; RUN: llc < %s -march=x86 -mcpu=core2 -pre-RA-sched=source -enable-misched -verify-misched -debug-only=misched -o - 2>&1 > /dev/null | FileCheck %s
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;
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; Test scheduling of copy instructions.
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;
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; Argument copies should be hoisted to the top of the block.
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; Return copies should be sunk to the end.
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; MUL_HiLo PhysReg use copies should be just above the mul.
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; MUL_HiLo PhysReg def copies should be just below the mul.
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;
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; CHECK: *** Final schedule for BB#1 ***
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; CHECK: %EAX<def> = COPY
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; CHECK-NEXT: MUL32r %vreg{{[0-9]+}}, %EAX<imp-def>, %EDX<imp-def>, %EFLAGS<imp-def,dead>, %EAX<imp-use>;
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; CHECK-NEXT: COPY %E{{[AD]}}X
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; CHECK-NEXT: COPY %E{{[AD]}}X
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; CHECK: DIVSSrm
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define i64 @mulhoist(i32 %a, i32 %b) #0 {
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entry:
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br label %body
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body:
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%convb = sitofp i32 %b to float
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; Generates an iMUL64r to legalize types.
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%aa = zext i32 %a to i64
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%mul = mul i64 %aa, 74383
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; Do some dependent long latency stuff.
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%trunc = trunc i64 %mul to i32
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%convm = sitofp i32 %trunc to float
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%divm = fdiv float %convm, 0.75
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;%addmb = fadd float %divm, %convb
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;%divmb = fdiv float %addmb, 0.125
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; Do some independent long latency stuff.
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%conva = sitofp i32 %a to float
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%diva = fdiv float %conva, 0.75
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%addab = fadd float %diva, %convb
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%divab = fdiv float %addab, 0.125
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br label %end
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end:
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%val = fptosi float %divab to i64
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%add = add i64 %mul, %val
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ret i64 %add
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}
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attributes #0 = { nounwind ssp uwtable "less-precise-fpmad"="false" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" }
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!0 = metadata !{metadata !"float", metadata !1}
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!1 = metadata !{metadata !"omnipotent char", metadata !2}
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!2 = metadata !{metadata !"Simple C/C++ TBAA"}
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