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ee87f9f4e2
Used to model structural hazards on FP issue, where some instructions take up 2 issue slots and others one as well as similar structural hazards on load issue, where some instructions take up two load lanes and others one. Differential Revision: https://reviews.llvm.org/D98977
76 lines
3.0 KiB
ArmAsm
76 lines
3.0 KiB
ArmAsm
# NOTE: Assertions have been autogenerated by utils/update_mca_test_checks.py
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# RUN: llvm-mca -mtriple=arm -mcpu=cortex-m7 --timeline --iterations=1 < %s | FileCheck %s
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add r1, r1, #1
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# ReadAdvance: 0
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add r1, r1, #2
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# ReadAdvance: -1
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vldr d0, [r1]
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# CHECK: Iterations: 1
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# CHECK-NEXT: Instructions: 3
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# CHECK-NEXT: Total Cycles: 6
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# CHECK-NEXT: Total uOps: 3
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# CHECK: Dispatch Width: 2
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# CHECK-NEXT: uOps Per Cycle: 0.50
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# CHECK-NEXT: IPC: 0.50
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# CHECK-NEXT: Block RThroughput: 1.5
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# CHECK: Instruction Info:
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# CHECK-NEXT: [1]: #uOps
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# CHECK-NEXT: [2]: Latency
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# CHECK-NEXT: [3]: RThroughput
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# CHECK-NEXT: [4]: MayLoad
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# CHECK-NEXT: [5]: MayStore
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# CHECK-NEXT: [6]: HasSideEffects (U)
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# CHECK: [1] [2] [3] [4] [5] [6] Instructions:
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# CHECK-NEXT: 1 1 0.50 add.w r1, r1, #1
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# CHECK-NEXT: 1 1 0.50 add.w r1, r1, #2
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# CHECK-NEXT: 1 3 1.00 * vldr d0, [r1]
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# CHECK: Resources:
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# CHECK-NEXT: [0.0] - M7UnitALU
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# CHECK-NEXT: [0.1] - M7UnitALU
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# CHECK-NEXT: [1] - M7UnitBranch
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# CHECK-NEXT: [2] - M7UnitLoadH
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# CHECK-NEXT: [3] - M7UnitLoadL
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# CHECK-NEXT: [4] - M7UnitMAC
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# CHECK-NEXT: [5] - M7UnitSIMD
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# CHECK-NEXT: [6] - M7UnitShift1
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# CHECK-NEXT: [7] - M7UnitShift2
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# CHECK-NEXT: [8] - M7UnitStore
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# CHECK-NEXT: [9] - M7UnitVFP
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# CHECK-NEXT: [10] - M7UnitVPortH
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# CHECK-NEXT: [11] - M7UnitVPortL
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# CHECK: Resource pressure per iteration:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11]
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# CHECK-NEXT: 1.00 1.00 - 1.00 1.00 - - - - - - 1.00 1.00
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# CHECK: Resource pressure by instruction:
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# CHECK-NEXT: [0.0] [0.1] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] Instructions:
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# CHECK-NEXT: - 1.00 - - - - - - - - - - - add.w r1, r1, #1
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# CHECK-NEXT: 1.00 - - - - - - - - - - - - add.w r1, r1, #2
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# CHECK-NEXT: - - - 1.00 1.00 - - - - - - 1.00 1.00 vldr d0, [r1]
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# CHECK: Timeline view:
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# CHECK-NEXT: Index 012345
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# CHECK: [0,0] DE . add.w r1, r1, #1
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# CHECK-NEXT: [0,1] .DE . add.w r1, r1, #2
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# CHECK-NEXT: [0,2] . DeE vldr d0, [r1]
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# CHECK: Average Wait times (based on the timeline view):
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# CHECK-NEXT: [0]: Executions
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# CHECK-NEXT: [1]: Average time spent waiting in a scheduler's queue
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# CHECK-NEXT: [2]: Average time spent waiting in a scheduler's queue while ready
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# CHECK-NEXT: [3]: Average time elapsed from WB until retire stage
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# CHECK: [0] [1] [2] [3]
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# CHECK-NEXT: 0. 1 0.0 0.0 0.0 add.w r1, r1, #1
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# CHECK-NEXT: 1. 1 0.0 0.0 0.0 add.w r1, r1, #2
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# CHECK-NEXT: 2. 1 0.0 0.0 0.0 vldr d0, [r1]
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# CHECK-NEXT: 1 0.0 0.0 0.0 <total>
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