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8a40b05b65
Summary: During legalization if i16, do not ASSERTZEXT the result of FP_TO_FP16. Directly return an FP_TO_FP16 node with return type as the promote-to-type of i16. This patch also removes extraneous length check. This legalization should be valid even if integer and float types are of different lengths. This patch breaks a hard-float test for fp16 args. The test is changed to allow a vmov to zero-out the top bits, and also ensure that the return value is in an FP register. Reviewers: ab, jmolloy Subscribers: srhines, llvm-commits Differential Revision: http://reviews.llvm.org/D15438 llvm-svn: 257184
42 lines
1.5 KiB
LLVM
42 lines
1.5 KiB
LLVM
; RUN: llc -float-abi soft -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=SOFT
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; RUN: llc -float-abi hard -mattr=+fp16 < %s | FileCheck %s --check-prefix=CHECK --check-prefix=HARD
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target datalayout = "e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64"
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target triple = "armv7a--none-eabi"
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define float @foo(float %a.coerce, float %b.coerce) {
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entry:
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%0 = bitcast float %a.coerce to i32
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%tmp.0.extract.trunc = trunc i32 %0 to i16
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%1 = bitcast i16 %tmp.0.extract.trunc to half
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%2 = bitcast float %b.coerce to i32
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%tmp1.0.extract.trunc = trunc i32 %2 to i16
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%3 = bitcast i16 %tmp1.0.extract.trunc to half
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%4 = fadd half %1, %3
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%5 = bitcast half %4 to i16
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%tmp5.0.insert.ext = zext i16 %5 to i32
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%6 = bitcast i32 %tmp5.0.insert.ext to float
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ret float %6
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; CHECK: foo:
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; SOFT: vmov {{s[0-9]+}}, r1
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; SOFT: vmov {{s[0-9]+}}, r0
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; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
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; SOFT: vcvtb.f32.f16 {{s[0-9]+}}, {{s[0-9]+}}
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; SOFT: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; SOFT: vcvtb.f16.f32 {{s[0-9]+}}, {{s[0-9]+}}
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; SOFT: vmov r0, {{s[0-9]+}}
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; HARD-NOT: vmov
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; HARD-NOT: uxth
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; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s1
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; HARD: vcvtb.f32.f16 {{s[0-9]+}}, s0
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; HARD: vadd.f32 {{s[0-9]+}}, {{s[0-9]+}}, {{s[0-9]+}}
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; HARD: vcvtb.f16.f32 [[SREG:s[0-9]+]], {{s[0-9]+}}
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; HARD-NEXT: vmov [[REG0:r[0-9]+]], [[SREG]]
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; HARD-NEXT: uxth [[REG1:r[0-9]+]], [[REG0]]
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; HARD-NEXT: vmov s0, [[REG1]]
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; CHECK: bx lr
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}
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