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859dccec1f
More updating of tests to be explicit about the target triple rather than relying on the default target triple supporting ARM mode. Indicate to lit that object emission is not yet available for Windows on ARM. llvm-svn: 205545
15 lines
398 B
LLVM
15 lines
398 B
LLVM
; RUN: llc -mtriple=arm-eabi -mcpu=cortex-a8 %s -o - | FileCheck %s
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define i32 @f(i32 %a, i32 %b, i32 %c) nounwind readnone ssp {
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entry:
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; CHECK-NOT: smmls
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%conv4 = zext i32 %a to i64
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%conv1 = sext i32 %b to i64
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%conv2 = sext i32 %c to i64
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%mul = mul nsw i64 %conv2, %conv1
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%shr5 = lshr i64 %mul, 32
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%sub = sub nsw i64 %conv4, %shr5
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%conv3 = trunc i64 %sub to i32
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ret i32 %conv3
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}
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