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9313cc801d
Current powerpc backend generates wrong code sequence if stack pointer has to realign if `-fstack-clash-protection` enabled. When probing dynamic stack allocation, current `PREPARE_PROBED_ALLOCA` takes `NegSizeReg` as input and returns `FinalStackPtr`. `FinalStackPtr=StackPtr+ActualNegSize` is calculated correctly, however code following `PREPARE_PROBED_ALLOCA` still uses value of `NegSizeReg`, which does not contain `ActualNegSize` if `MaxAlign > TargetAlign`, to calculate loop trip count and residual number of bytes. This patch is part of fix of https://bugs.llvm.org/show_bug.cgi?id=46759. Differential Revision: https://reviews.llvm.org/D84152
60 lines
2.0 KiB
LLVM
60 lines
2.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-linux-gnu < %s | FileCheck \
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; RUN: -check-prefix=CHECK-LE %s
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define void @foo(i32 %vla_size) #0 {
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; CHECK-LE-LABEL: foo:
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; CHECK-LE: # %bb.0: # %entry
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; CHECK-LE-NEXT: std r31, -8(r1)
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; CHECK-LE-NEXT: std r30, -16(r1)
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; CHECK-LE-NEXT: mr r30, r1
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; CHECK-LE-NEXT: mr r12, r1
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; CHECK-LE-NEXT: .cfi_def_cfa r12, 0
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; CHECK-LE-NEXT: clrldi r0, r12, 53
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; CHECK-LE-NEXT: subc r1, r1, r0
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; CHECK-LE-NEXT: stdu r12, -2048(r1)
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; CHECK-LE-NEXT: stdu r12, -4096(r1)
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; CHECK-LE-NEXT: .cfi_def_cfa_register r1
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; CHECK-LE-NEXT: .cfi_def_cfa_register r30
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; CHECK-LE-NEXT: .cfi_offset r31, -8
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; CHECK-LE-NEXT: .cfi_offset r30, -16
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; CHECK-LE-NEXT: clrldi r3, r3, 32
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; CHECK-LE-NEXT: li r5, -2048
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; CHECK-LE-NEXT: mr r31, r1
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; CHECK-LE-NEXT: addi r3, r3, 15
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; CHECK-LE-NEXT: rldicl r3, r3, 60, 4
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; CHECK-LE-NEXT: rldicl r3, r3, 4, 31
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; CHECK-LE-NEXT: neg r4, r3
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; CHECK-LE-NEXT: ld r3, 0(r1)
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; CHECK-LE-NEXT: and r5, r4, r5
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; CHECK-LE-NEXT: mr r4, r5
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; CHECK-LE-NEXT: li r5, -4096
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; CHECK-LE-NEXT: divd r6, r4, r5
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; CHECK-LE-NEXT: mulld r5, r6, r5
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; CHECK-LE-NEXT: sub r5, r4, r5
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; CHECK-LE-NEXT: add r4, r1, r4
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; CHECK-LE-NEXT: stdux r3, r1, r5
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; CHECK-LE-NEXT: cmpd r1, r4
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; CHECK-LE-NEXT: beq cr0, .LBB0_2
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; CHECK-LE-NEXT: .LBB0_1: # %entry
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; CHECK-LE-NEXT: #
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; CHECK-LE-NEXT: stdu r3, -4096(r1)
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; CHECK-LE-NEXT: cmpd r1, r4
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; CHECK-LE-NEXT: bne cr0, .LBB0_1
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; CHECK-LE-NEXT: .LBB0_2: # %entry
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; CHECK-LE-NEXT: addi r3, r1, 2048
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; CHECK-LE-NEXT: lbz r3, 0(r3)
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; CHECK-LE-NEXT: ld r1, 0(r1)
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; CHECK-LE-NEXT: ld r31, -8(r1)
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; CHECK-LE-NEXT: ld r30, -16(r1)
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; CHECK-LE-NEXT: blr
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entry:
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%0 = zext i32 %vla_size to i64
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%vla = alloca i8, i64 %0, align 2048
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%1 = load volatile i8, i8* %vla, align 2048
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ret void
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}
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attributes #0 = { "probe-stack"="inline-asm" }
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