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c5ee99bbd2
Summary: Currently, MachineVerifier will attempt to verify that tied operands satisfy register constraints as soon as the function is no longer in SSA form. However, PHIElimination will take the function out of SSA form while TwoAddressInstructionPass will actually rewrite tied operands to match the constraints. PHIElimination runs first in the pipeline. Therefore, whenever the MachineVerifier is run after PHIElimination, it will encounter verification errors on any tied operands. This patch adds a function property called TiedOpsRewritten that will be set by TwoAddressInstructionPass and will control when the verifier checks tied operands. Reviewed By: nemanjai Differential Revision: https://reviews.llvm.org/D80538
101 lines
3.3 KiB
YAML
101 lines
3.3 KiB
YAML
# RUN: llc -mtriple=ppc32-- %s -run-pass=phi-node-elimination \
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# RUN: -verify-machineinstrs -o /dev/null 2>&1
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# RUN: llc -mtriple=ppc32-- %s -start-before=phi-node-elimination \
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# RUN: -verify-machineinstrs -o /dev/null 2>&1
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--- |
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define void @VerifyTwoAddressCrash(i16 %div.0.i.i.i.i, i32 %L_num.0.i.i.i.i, i32 %tmp1.i.i206.i.i, i16* %P) {
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%X = shl i16 %div.0.i.i.i.i, 1
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%tmp28.i.i.i.i = shl i32 %L_num.0.i.i.i.i, 1
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%tmp31.i.i.i.i = icmp slt i32 %tmp28.i.i.i.i, %tmp1.i.i206.i.i
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%tmp31.i.i.i.i.upgrd.1 = zext i1 %tmp31.i.i.i.i to i16
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%tmp371.i.i.i.i1 = or i16 %tmp31.i.i.i.i.upgrd.1, %X
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%div.0.be.i.i.i.i = xor i16 %tmp371.i.i.i.i1, 1
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store i16 %div.0.be.i.i.i.i, i16* %P, align 2
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ret void
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}
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...
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---
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name: VerifyTwoAddressCrash
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alignment: 4
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exposesReturnsTwice: false
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legalized: false
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regBankSelected: false
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selected: false
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failedISel: false
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tracksRegLiveness: true
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hasWinCFI: false
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registers:
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- { id: 0, class: gprc, preferred-register: '' }
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- { id: 1, class: gprc, preferred-register: '' }
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- { id: 2, class: gprc, preferred-register: '' }
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- { id: 3, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 4, class: gprc, preferred-register: '' }
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- { id: 5, class: crrc, preferred-register: '' }
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- { id: 6, class: crbitrc, preferred-register: '' }
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- { id: 7, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 8, class: gprc_and_gprc_nor0, preferred-register: '' }
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- { id: 9, class: gprc, preferred-register: '' }
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- { id: 10, class: gprc, preferred-register: '' }
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- { id: 11, class: gprc, preferred-register: '' }
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liveins:
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- { reg: '$r3', virtual-reg: '%0' }
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- { reg: '$r4', virtual-reg: '%1' }
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- { reg: '$r5', virtual-reg: '%2' }
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- { reg: '$r6', virtual-reg: '%3' }
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frameInfo:
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isFrameAddressTaken: false
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isReturnAddressTaken: false
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hasStackMap: false
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hasPatchPoint: false
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stackSize: 0
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offsetAdjustment: 0
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maxAlignment: 4
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adjustsStack: false
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hasCalls: false
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stackProtector: ''
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maxCallFrameSize: 4294967295
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cvBytesOfCalleeSavedRegisters: 0
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hasOpaqueSPAdjustment: false
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hasVAStart: false
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hasMustTailInVarArgFunc: false
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localFrameSize: 0
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savePoint: ''
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restorePoint: ''
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fixedStack: []
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stack: []
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callSites: []
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constants: []
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machineFunctionInfo: {}
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body: |
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bb.0 (%ir-block.0):
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liveins: $r3, $r4, $r5, $r6
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%3:gprc_and_gprc_nor0 = COPY killed $r6
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%2:gprc = COPY killed $r5
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%1:gprc = COPY killed $r4
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%0:gprc = COPY killed $r3
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%4:gprc = RLWINM killed %1, 1, 0, 30
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%5:crrc = CMPW killed %4, killed %2
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%6:crbitrc = COPY killed %5.sub_lt
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%7:gprc_and_gprc_nor0 = LI 0
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%8:gprc_and_gprc_nor0 = LI 1
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%9:gprc = ISEL killed %8, killed %7, killed %6
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%10:gprc = RLWIMI killed %9, killed %0, 1, 0, 30
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%11:gprc = XORI killed %10, 1
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STH killed %11, 0, killed %3 :: (store 2 into %ir.P)
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BLR implicit $lr, implicit $rm
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...
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# Used to result in
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#
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# Bad machine code: Two-address instruction operands must be identical
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# - function: VerifyTwoAddressCrash
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# - basic block: %bb.0
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# - instruction: %10:gprc = RLWIMI killed %9:gprc(tied-def 0), killed %0:gprc, 1, 0, 30
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# - operand 1: killed %9:gprc(tied-def 0)
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# LLVM ERROR: Found 1 machine code errors.
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# Just verify that we do not crash (or get verifier error).
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