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651 lines
23 KiB
TableGen
651 lines
23 KiB
TableGen
//===- IntrinsicsAMDGPU.td - Defines AMDGPU intrinsics -----*- tablegen -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines all of the R600-specific intrinsics.
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//
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//===----------------------------------------------------------------------===//
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class AMDGPUReadPreloadRegisterIntrinsic
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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class AMDGPUReadPreloadRegisterIntrinsicNamed<string name>
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: Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>, GCCBuiltin<name>;
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let TargetPrefix = "r600" in {
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multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz {
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def _x : AMDGPUReadPreloadRegisterIntrinsic;
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def _y : AMDGPUReadPreloadRegisterIntrinsic;
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def _z : AMDGPUReadPreloadRegisterIntrinsic;
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}
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multiclass AMDGPUReadPreloadRegisterIntrinsic_xyz_named<string prefix> {
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def _x : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_x")>;
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def _y : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_y")>;
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def _z : AMDGPUReadPreloadRegisterIntrinsicNamed<!strconcat(prefix, "_z")>;
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}
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defm int_r600_read_global_size : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
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<"__builtin_r600_read_global_size">;
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defm int_r600_read_ngroups : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
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<"__builtin_r600_read_ngroups">;
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defm int_r600_read_tgid : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
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<"__builtin_r600_read_tgid">;
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defm int_r600_read_local_size : AMDGPUReadPreloadRegisterIntrinsic_xyz;
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defm int_r600_read_tidig : AMDGPUReadPreloadRegisterIntrinsic_xyz;
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def int_r600_group_barrier : GCCBuiltin<"__builtin_r600_group_barrier">,
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Intrinsic<[], [], [IntrConvergent]>;
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// AS 7 is PARAM_I_ADDRESS, used for kernel arguments
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def int_r600_implicitarg_ptr :
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GCCBuiltin<"__builtin_r600_implicitarg_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 7>], [], [IntrNoMem]>;
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def int_r600_rat_store_typed :
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// 1st parameter: Data
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// 2nd parameter: Index
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// 3rd parameter: Constant RAT ID
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Intrinsic<[], [llvm_v4i32_ty, llvm_v4i32_ty, llvm_i32_ty], []>,
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GCCBuiltin<"__builtin_r600_rat_store_typed">;
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def int_r600_recipsqrt_ieee : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_r600_recipsqrt_clamped : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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} // End TargetPrefix = "r600"
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let TargetPrefix = "amdgcn" in {
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//===----------------------------------------------------------------------===//
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// ABI Special Intrinsics
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//===----------------------------------------------------------------------===//
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defm int_amdgcn_workitem_id : AMDGPUReadPreloadRegisterIntrinsic_xyz;
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defm int_amdgcn_workgroup_id : AMDGPUReadPreloadRegisterIntrinsic_xyz_named
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<"__builtin_amdgcn_workgroup_id">;
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def int_amdgcn_dispatch_ptr :
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GCCBuiltin<"__builtin_amdgcn_dispatch_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;
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def int_amdgcn_queue_ptr :
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GCCBuiltin<"__builtin_amdgcn_queue_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;
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def int_amdgcn_kernarg_segment_ptr :
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GCCBuiltin<"__builtin_amdgcn_kernarg_segment_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;
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def int_amdgcn_implicitarg_ptr :
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GCCBuiltin<"__builtin_amdgcn_implicitarg_ptr">,
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Intrinsic<[LLVMQualPointerType<llvm_i8_ty, 2>], [], [IntrNoMem]>;
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def int_amdgcn_groupstaticsize :
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GCCBuiltin<"__builtin_amdgcn_groupstaticsize">,
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Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
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def int_amdgcn_dispatch_id :
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GCCBuiltin<"__builtin_amdgcn_dispatch_id">,
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Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
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//===----------------------------------------------------------------------===//
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// Instruction Intrinsics
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//===----------------------------------------------------------------------===//
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// The first parameter is s_sendmsg immediate (i16),
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// the second one is copied to m0
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def int_amdgcn_s_sendmsg : GCCBuiltin<"__builtin_amdgcn_s_sendmsg">,
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Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_amdgcn_s_sendmsghalt : GCCBuiltin<"__builtin_amdgcn_s_sendmsghalt">,
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Intrinsic <[], [llvm_i32_ty, llvm_i32_ty], []>;
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def int_amdgcn_s_barrier : GCCBuiltin<"__builtin_amdgcn_s_barrier">,
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Intrinsic<[], [], [IntrConvergent]>;
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def int_amdgcn_wave_barrier : GCCBuiltin<"__builtin_amdgcn_wave_barrier">,
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Intrinsic<[], [], [IntrConvergent]>;
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def int_amdgcn_s_waitcnt : Intrinsic<[], [llvm_i32_ty], []>;
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def int_amdgcn_div_scale : Intrinsic<
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// 1st parameter: Numerator
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// 2nd parameter: Denominator
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// 3rd parameter: Constant to select select between first and
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// second. (0 = first, 1 = second).
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[llvm_anyfloat_ty, llvm_i1_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]
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>;
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def int_amdgcn_div_fmas : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>, llvm_i1_ty],
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[IntrNoMem]
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>;
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def int_amdgcn_div_fixup : Intrinsic<[llvm_anyfloat_ty],
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[LLVMMatchType<0>, LLVMMatchType<0>, LLVMMatchType<0>],
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[IntrNoMem]
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>;
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def int_amdgcn_trig_preop : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_sin : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_cos : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_log_clamp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_fmul_legacy : GCCBuiltin<"__builtin_amdgcn_fmul_legacy">,
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Intrinsic<[llvm_float_ty], [llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_rcp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_rcp_legacy : GCCBuiltin<"__builtin_amdgcn_rcp_legacy">,
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Intrinsic<[llvm_float_ty], [llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_rsq : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_rsq_legacy : GCCBuiltin<"__builtin_amdgcn_rsq_legacy">,
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Intrinsic<
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[llvm_float_ty], [llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_rsq_clamp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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def int_amdgcn_ldexp : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_frexp_mant : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_frexp_exp : Intrinsic<
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[llvm_anyint_ty], [llvm_anyfloat_ty], [IntrNoMem]
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>;
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// v_fract is buggy on SI/CI. It mishandles infinities, may return 1.0
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// and always uses rtz, so is not suitable for implementing the OpenCL
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// fract function. It should be ok on VI.
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def int_amdgcn_fract : Intrinsic<
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[llvm_anyfloat_ty], [LLVMMatchType<0>], [IntrNoMem]
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>;
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def int_amdgcn_class : Intrinsic<
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[llvm_i1_ty], [llvm_anyfloat_ty, llvm_i32_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubeid : GCCBuiltin<"__builtin_amdgcn_cubeid">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubema : GCCBuiltin<"__builtin_amdgcn_cubema">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubesc : GCCBuiltin<"__builtin_amdgcn_cubesc">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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def int_amdgcn_cubetc : GCCBuiltin<"__builtin_amdgcn_cubetc">,
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Intrinsic<[llvm_float_ty],
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[llvm_float_ty, llvm_float_ty, llvm_float_ty], [IntrNoMem]
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>;
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// v_ffbh_i32, as opposed to v_ffbh_u32. For v_ffbh_u32, llvm.ctlz
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// should be used.
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def int_amdgcn_sffbh :
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Intrinsic<[llvm_anyint_ty], [LLVMMatchType<0>], [IntrNoMem]>;
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// TODO: Do we want an ordering for these?
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def int_amdgcn_atomic_inc : Intrinsic<[llvm_anyint_ty],
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[llvm_anyptr_ty, LLVMMatchType<0>],
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[IntrArgMemOnly, NoCapture<0>]
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>;
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def int_amdgcn_atomic_dec : Intrinsic<[llvm_anyint_ty],
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[llvm_anyptr_ty, LLVMMatchType<0>],
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[IntrArgMemOnly, NoCapture<0>]
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>;
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class AMDGPUImageLoad : Intrinsic <
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[llvm_anyfloat_ty], // vdata(VGPR)
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[llvm_anyint_ty, // vaddr(VGPR)
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llvm_anyint_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty, // slc(imm)
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llvm_i1_ty, // lwe(imm)
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llvm_i1_ty], // da(imm)
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[IntrReadMem]>;
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def int_amdgcn_image_load : AMDGPUImageLoad;
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def int_amdgcn_image_load_mip : AMDGPUImageLoad;
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def int_amdgcn_image_getresinfo : AMDGPUImageLoad;
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class AMDGPUImageStore : Intrinsic <
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[],
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[llvm_anyfloat_ty, // vdata(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_anyint_ty, // rsrc(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty, // slc(imm)
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llvm_i1_ty, // lwe(imm)
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llvm_i1_ty], // da(imm)
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[]>;
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def int_amdgcn_image_store : AMDGPUImageStore;
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def int_amdgcn_image_store_mip : AMDGPUImageStore;
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class AMDGPUImageSample : Intrinsic <
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[llvm_anyfloat_ty], // vdata(VGPR)
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[llvm_anyfloat_ty, // vaddr(VGPR)
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llvm_anyint_ty, // rsrc(SGPR)
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llvm_v4i32_ty, // sampler(SGPR)
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llvm_i32_ty, // dmask(imm)
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llvm_i1_ty, // unorm(imm)
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llvm_i1_ty, // glc(imm)
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llvm_i1_ty, // slc(imm)
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llvm_i1_ty, // lwe(imm)
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llvm_i1_ty], // da(imm)
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[IntrReadMem]>;
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// Basic sample
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def int_amdgcn_image_sample : AMDGPUImageSample;
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def int_amdgcn_image_sample_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_d : AMDGPUImageSample;
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def int_amdgcn_image_sample_d_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_l : AMDGPUImageSample;
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def int_amdgcn_image_sample_b : AMDGPUImageSample;
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def int_amdgcn_image_sample_b_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_lz : AMDGPUImageSample;
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def int_amdgcn_image_sample_cd : AMDGPUImageSample;
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def int_amdgcn_image_sample_cd_cl : AMDGPUImageSample;
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// Sample with comparison
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def int_amdgcn_image_sample_c : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_d : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_d_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_l : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_b : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_b_cl : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_lz : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cd : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cd_cl : AMDGPUImageSample;
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// Sample with offsets
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def int_amdgcn_image_sample_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_d_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_d_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_l_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_b_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_b_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_lz_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_cd_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_cd_cl_o : AMDGPUImageSample;
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// Sample with comparison and offsets
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def int_amdgcn_image_sample_c_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_d_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_d_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_l_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_b_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_b_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_lz_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cd_o : AMDGPUImageSample;
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def int_amdgcn_image_sample_c_cd_cl_o : AMDGPUImageSample;
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// Basic gather4
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def int_amdgcn_image_gather4 : AMDGPUImageSample;
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def int_amdgcn_image_gather4_cl : AMDGPUImageSample;
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def int_amdgcn_image_gather4_l : AMDGPUImageSample;
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def int_amdgcn_image_gather4_b : AMDGPUImageSample;
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def int_amdgcn_image_gather4_b_cl : AMDGPUImageSample;
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def int_amdgcn_image_gather4_lz : AMDGPUImageSample;
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// Gather4 with comparison
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def int_amdgcn_image_gather4_c : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_cl : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_l : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_b : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_b_cl : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_lz : AMDGPUImageSample;
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// Gather4 with offsets
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def int_amdgcn_image_gather4_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_l_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_b_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_b_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_lz_o : AMDGPUImageSample;
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// Gather4 with comparison and offsets
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def int_amdgcn_image_gather4_c_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_l_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_b_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_b_cl_o : AMDGPUImageSample;
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def int_amdgcn_image_gather4_c_lz_o : AMDGPUImageSample;
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def int_amdgcn_image_getlod : AMDGPUImageSample;
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class AMDGPUImageAtomic : Intrinsic <
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[llvm_i32_ty],
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[llvm_i32_ty, // vdata(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
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llvm_v8i32_ty, // rsrc(SGPR)
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llvm_i1_ty, // r128(imm)
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llvm_i1_ty, // da(imm)
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llvm_i1_ty], // slc(imm)
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[]>;
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def int_amdgcn_image_atomic_swap : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_add : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_sub : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_smin : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_umin : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_smax : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_umax : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_and : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_or : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_xor : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_inc : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_dec : AMDGPUImageAtomic;
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def int_amdgcn_image_atomic_cmpswap : Intrinsic <
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[llvm_i32_ty],
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[llvm_i32_ty, // src(VGPR)
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llvm_i32_ty, // cmp(VGPR)
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llvm_anyint_ty, // vaddr(VGPR)
|
|
llvm_v8i32_ty, // rsrc(SGPR)
|
|
llvm_i1_ty, // r128(imm)
|
|
llvm_i1_ty, // da(imm)
|
|
llvm_i1_ty], // slc(imm)
|
|
[]>;
|
|
|
|
class AMDGPUBufferLoad : Intrinsic <
|
|
[llvm_anyfloat_ty],
|
|
[llvm_v4i32_ty, // rsrc(SGPR)
|
|
llvm_i32_ty, // vindex(VGPR)
|
|
llvm_i32_ty, // offset(SGPR/VGPR/imm)
|
|
llvm_i1_ty, // glc(imm)
|
|
llvm_i1_ty], // slc(imm)
|
|
[IntrReadMem]>;
|
|
def int_amdgcn_buffer_load_format : AMDGPUBufferLoad;
|
|
def int_amdgcn_buffer_load : AMDGPUBufferLoad;
|
|
|
|
class AMDGPUBufferStore : Intrinsic <
|
|
[],
|
|
[llvm_anyfloat_ty, // vdata(VGPR) -- can currently only select f32, v2f32, v4f32
|
|
llvm_v4i32_ty, // rsrc(SGPR)
|
|
llvm_i32_ty, // vindex(VGPR)
|
|
llvm_i32_ty, // offset(SGPR/VGPR/imm)
|
|
llvm_i1_ty, // glc(imm)
|
|
llvm_i1_ty], // slc(imm)
|
|
[IntrWriteMem]>;
|
|
def int_amdgcn_buffer_store_format : AMDGPUBufferStore;
|
|
def int_amdgcn_buffer_store : AMDGPUBufferStore;
|
|
|
|
class AMDGPUBufferAtomic : Intrinsic <
|
|
[llvm_i32_ty],
|
|
[llvm_i32_ty, // vdata(VGPR)
|
|
llvm_v4i32_ty, // rsrc(SGPR)
|
|
llvm_i32_ty, // vindex(VGPR)
|
|
llvm_i32_ty, // offset(SGPR/VGPR/imm)
|
|
llvm_i1_ty], // slc(imm)
|
|
[]>;
|
|
def int_amdgcn_buffer_atomic_swap : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_add : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_sub : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_smin : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_umin : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_smax : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_umax : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_and : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_or : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_xor : AMDGPUBufferAtomic;
|
|
def int_amdgcn_buffer_atomic_cmpswap : Intrinsic<
|
|
[llvm_i32_ty],
|
|
[llvm_i32_ty, // src(VGPR)
|
|
llvm_i32_ty, // cmp(VGPR)
|
|
llvm_v4i32_ty, // rsrc(SGPR)
|
|
llvm_i32_ty, // vindex(VGPR)
|
|
llvm_i32_ty, // offset(SGPR/VGPR/imm)
|
|
llvm_i1_ty], // slc(imm)
|
|
[]>;
|
|
|
|
// Uses that do not set the done bit should set IntrWriteMem on the
|
|
// call site.
|
|
def int_amdgcn_exp : Intrinsic <[], [
|
|
llvm_i32_ty, // tgt,
|
|
llvm_i32_ty, // en
|
|
llvm_any_ty, // src0 (f32 or i32)
|
|
LLVMMatchType<0>, // src1
|
|
LLVMMatchType<0>, // src2
|
|
LLVMMatchType<0>, // src3
|
|
llvm_i1_ty, // done
|
|
llvm_i1_ty // vm
|
|
],
|
|
[]
|
|
>;
|
|
|
|
// exp with compr bit set.
|
|
def int_amdgcn_exp_compr : Intrinsic <[], [
|
|
llvm_i32_ty, // tgt,
|
|
llvm_i32_ty, // en
|
|
llvm_anyvector_ty, // src0 (v2f16 or v2i16)
|
|
LLVMMatchType<0>, // src1
|
|
llvm_i1_ty, // done
|
|
llvm_i1_ty], // vm
|
|
[]
|
|
>;
|
|
|
|
def int_amdgcn_buffer_wbinvl1_sc :
|
|
GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_sc">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_buffer_wbinvl1 :
|
|
GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_s_dcache_inv :
|
|
GCCBuiltin<"__builtin_amdgcn_s_dcache_inv">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_s_memtime :
|
|
GCCBuiltin<"__builtin_amdgcn_s_memtime">,
|
|
Intrinsic<[llvm_i64_ty], [], []>;
|
|
|
|
def int_amdgcn_s_sleep :
|
|
GCCBuiltin<"__builtin_amdgcn_s_sleep">,
|
|
Intrinsic<[], [llvm_i32_ty], []> {
|
|
}
|
|
|
|
def int_amdgcn_s_incperflevel :
|
|
GCCBuiltin<"__builtin_amdgcn_s_incperflevel">,
|
|
Intrinsic<[], [llvm_i32_ty], []> {
|
|
}
|
|
|
|
def int_amdgcn_s_decperflevel :
|
|
GCCBuiltin<"__builtin_amdgcn_s_decperflevel">,
|
|
Intrinsic<[], [llvm_i32_ty], []> {
|
|
}
|
|
|
|
def int_amdgcn_s_getreg :
|
|
GCCBuiltin<"__builtin_amdgcn_s_getreg">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrReadMem]>;
|
|
|
|
// __builtin_amdgcn_interp_mov <param>, <attr_chan>, <attr>, <m0>
|
|
// param values: 0 = P10, 1 = P20, 2 = P0
|
|
def int_amdgcn_interp_mov :
|
|
GCCBuiltin<"__builtin_amdgcn_interp_mov">,
|
|
Intrinsic<[llvm_float_ty],
|
|
[llvm_i32_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
|
|
[IntrNoMem]>;
|
|
|
|
// __builtin_amdgcn_interp_p1 <i>, <attr_chan>, <attr>, <m0>
|
|
def int_amdgcn_interp_p1 :
|
|
GCCBuiltin<"__builtin_amdgcn_interp_p1">,
|
|
Intrinsic<[llvm_float_ty],
|
|
[llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
|
|
[IntrNoMem]>; // This intrinsic reads from lds, but the memory
|
|
// values are constant, so it behaves like IntrNoMem.
|
|
|
|
// __builtin_amdgcn_interp_p2 <p1>, <j>, <attr_chan>, <attr>, <m0>
|
|
def int_amdgcn_interp_p2 :
|
|
GCCBuiltin<"__builtin_amdgcn_interp_p2">,
|
|
Intrinsic<[llvm_float_ty],
|
|
[llvm_float_ty, llvm_float_ty, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty],
|
|
[IntrNoMem]>; // See int_amdgcn_v_interp_p1 for why this is
|
|
// IntrNoMem.
|
|
|
|
// Pixel shaders only: whether the current pixel is live (i.e. not a helper
|
|
// invocation for derivative computation).
|
|
def int_amdgcn_ps_live : Intrinsic <
|
|
[llvm_i1_ty],
|
|
[],
|
|
[IntrNoMem]>;
|
|
|
|
def int_amdgcn_mbcnt_lo :
|
|
GCCBuiltin<"__builtin_amdgcn_mbcnt_lo">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_mbcnt_hi :
|
|
GCCBuiltin<"__builtin_amdgcn_mbcnt_hi">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
// llvm.amdgcn.ds.swizzle src offset
|
|
def int_amdgcn_ds_swizzle :
|
|
GCCBuiltin<"__builtin_amdgcn_ds_swizzle">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
// llvm.amdgcn.lerp
|
|
def int_amdgcn_lerp :
|
|
GCCBuiltin<"__builtin_amdgcn_lerp">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_sad_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_sad_u8">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_msad_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_msad_u8">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_sad_hi_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_sad_hi_u8">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_sad_u16 :
|
|
GCCBuiltin<"__builtin_amdgcn_sad_u16">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_qsad_pk_u16_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_qsad_pk_u16_u8">,
|
|
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_mqsad_pk_u16_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_mqsad_pk_u16_u8">,
|
|
Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i32_ty, llvm_i64_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_mqsad_u32_u8 :
|
|
GCCBuiltin<"__builtin_amdgcn_mqsad_u32_u8">,
|
|
Intrinsic<[llvm_v4i32_ty], [llvm_i64_ty, llvm_i32_ty, llvm_v4i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_cvt_pk_u8_f32 :
|
|
GCCBuiltin<"__builtin_amdgcn_cvt_pk_u8_f32">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_float_ty, llvm_i32_ty, llvm_i32_ty], [IntrNoMem]>;
|
|
|
|
def int_amdgcn_icmp :
|
|
Intrinsic<[llvm_i64_ty], [llvm_anyint_ty, LLVMMatchType<0>, llvm_i32_ty],
|
|
[IntrNoMem, IntrConvergent]>;
|
|
|
|
def int_amdgcn_fcmp :
|
|
Intrinsic<[llvm_i64_ty], [llvm_anyfloat_ty, LLVMMatchType<0>, llvm_i32_ty],
|
|
[IntrNoMem, IntrConvergent]>;
|
|
|
|
def int_amdgcn_readfirstlane :
|
|
GCCBuiltin<"__builtin_amdgcn_readfirstlane">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
def int_amdgcn_readlane :
|
|
GCCBuiltin<"__builtin_amdgcn_readlane">,
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// CI+ Intrinsics
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def int_amdgcn_s_dcache_inv_vol :
|
|
GCCBuiltin<"__builtin_amdgcn_s_dcache_inv_vol">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_buffer_wbinvl1_vol :
|
|
GCCBuiltin<"__builtin_amdgcn_buffer_wbinvl1_vol">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// VI Intrinsics
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// llvm.amdgcn.mov.dpp.i32 <src> <dpp_ctrl> <row_mask> <bank_mask> <bound_ctrl>
|
|
def int_amdgcn_mov_dpp :
|
|
Intrinsic<[llvm_anyint_ty],
|
|
[LLVMMatchType<0>, llvm_i32_ty, llvm_i32_ty, llvm_i32_ty,
|
|
llvm_i1_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
def int_amdgcn_s_dcache_wb :
|
|
GCCBuiltin<"__builtin_amdgcn_s_dcache_wb">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_s_dcache_wb_vol :
|
|
GCCBuiltin<"__builtin_amdgcn_s_dcache_wb_vol">,
|
|
Intrinsic<[], [], []>;
|
|
|
|
def int_amdgcn_s_memrealtime :
|
|
GCCBuiltin<"__builtin_amdgcn_s_memrealtime">,
|
|
Intrinsic<[llvm_i64_ty], [], []>;
|
|
|
|
// llvm.amdgcn.ds.permute <index> <src>
|
|
def int_amdgcn_ds_permute :
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
// llvm.amdgcn.ds.bpermute <index> <src>
|
|
def int_amdgcn_ds_bpermute :
|
|
Intrinsic<[llvm_i32_ty], [llvm_i32_ty, llvm_i32_ty], [IntrNoMem, IntrConvergent]>;
|
|
|
|
}
|