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3633380341
Summary: In SelectionDAG, when a store is immediately chained to another store to the same address, elide the first store as it has no observable effects. This is causes small improvements dealing with intrinsics lowered to stores. Test notes: * Many testcases overwrite store addresses multiple times and needed minor changes, mainly making stores volatile to prevent the optimization from optimizing the test away. * Many X86 test cases optimized out instructions associated with associated with va_start. * Note that test_splat in CodeGen/AArch64/misched-stp.ll no longer has dependencies to check and can probably be removed and potentially replaced with another test. Reviewers: rnk, john.brawn Subscribers: aemerson, rengolin, qcolombet, jyknight, nemanjai, nhaehnle, javed.absar, llvm-commits Differential Revision: https://reviews.llvm.org/D33206 llvm-svn: 303198
136 lines
3.8 KiB
LLVM
136 lines
3.8 KiB
LLVM
; RUN: llc -mtriple=thumb-eabi < %s -o - | FileCheck %s
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; Check that stack addresses are generated using a single ADD
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define void @test1(i8** %p) {
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%x = alloca i8, align 1
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%y = alloca i8, align 1
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%z = alloca i8, align 1
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; CHECK: add r1, sp, #8
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; CHECK: str r1, [r0]
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store volatile i8* %x, i8** %p, align 4
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; CHECK: add r1, sp, #4
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; CHECK: str r1, [r0]
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store volatile i8* %y, i8** %p, align 4
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; CHECK: mov r1, sp
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; CHECK: str r1, [r0]
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store volatile i8* %z, i8** %p, align 4
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ret void
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}
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; Stack offsets larger than 1020 still need two ADDs
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define void @test2([1024 x i8]** %p) {
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%arr1 = alloca [1024 x i8], align 1
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%arr2 = alloca [1024 x i8], align 1
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; CHECK: add r1, sp, #1020
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; CHECK: adds r1, #4
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; CHECK: str r1, [r0]
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store volatile [1024 x i8]* %arr1, [1024 x i8]** %p, align 4
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; CHECK: mov r1, sp
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; CHECK: str r1, [r0]
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store volatile [1024 x i8]* %arr2, [1024 x i8]** %p, align 4
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ret void
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}
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; If possible stack-based lrdb/ldrh are widened to use SP-based addressing
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define i32 @test3() #0 {
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%x = alloca i8, align 1
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%y = alloca i8, align 1
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; CHECK: ldr r0, [sp]
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%1 = load i8, i8* %x, align 1
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; CHECK: ldr r1, [sp, #4]
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%2 = load i8, i8* %y, align 1
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%3 = add nsw i8 %1, %2
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%4 = zext i8 %3 to i32
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ret i32 %4
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}
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define i32 @test4() #0 {
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%x = alloca i16, align 2
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%y = alloca i16, align 2
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; CHECK: ldr r0, [sp]
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%1 = load i16, i16* %x, align 2
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; CHECK: ldr r1, [sp, #4]
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%2 = load i16, i16* %y, align 2
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%3 = add nsw i16 %1, %2
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%4 = zext i16 %3 to i32
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ret i32 %4
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}
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; Don't widen if the value needs to be zero-extended
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define zeroext i8 @test5() {
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%x = alloca i8, align 1
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; CHECK: mov r0, sp
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; CHECK: ldrb r0, [r0]
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%1 = load i8, i8* %x, align 1
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ret i8 %1
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}
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define zeroext i16 @test6() {
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%x = alloca i16, align 2
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; CHECK: mov r0, sp
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; CHECK: ldrh r0, [r0]
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%1 = load i16, i16* %x, align 2
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ret i16 %1
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}
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; Accessing the bottom of a large array shouldn't require materializing a base
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;
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; CHECK: movs [[REG:r[0-9]+]], #1
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; CHECK: str [[REG]], [sp, #16]
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; CHECK: str [[REG]], [sp, #4]
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define void @test7() {
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%arr = alloca [200 x i32], align 4
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%arrayidx = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 1
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store i32 1, i32* %arrayidx, align 4
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%arrayidx1 = getelementptr inbounds [200 x i32], [200 x i32]* %arr, i32 0, i32 4
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store i32 1, i32* %arrayidx1, align 4
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ret void
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}
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; Check that loads/stores with out-of-range offsets are handled correctly
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define void @test8() {
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%arr3 = alloca [224 x i32], align 4
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%arr2 = alloca [224 x i32], align 4
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%arr1 = alloca [224 x i32], align 4
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; CHECK: movs [[REG:r[0-9]+]], #1
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; CHECK-DAG: str [[REG]], [sp]
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%arr1idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 0
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store i32 1, i32* %arr1idx1, align 4
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; Offset in range for sp-based store, but not for non-sp-based store
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; CHECK-DAG: str [[REG]], [sp, #128]
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%arr1idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr1, i32 0, i32 32
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store i32 1, i32* %arr1idx2, align 4
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; CHECK-DAG: str [[REG]], [sp, #896]
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%arr2idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 0
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store i32 1, i32* %arr2idx1, align 4
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; %arr2 is in range, but this element of it is not
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; CHECK-DAG: ldr [[RA:r[0-9]+]], .LCPI7_2
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; CHECK-DAG: add [[RA]], sp
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; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]
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%arr2idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr2, i32 0, i32 32
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store i32 1, i32* %arr2idx2, align 4
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; %arr3 is not in range
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; CHECK-DAG: ldr [[RB:r[0-9]+]], .LCPI7_3
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; CHECK-DAG: add [[RB]], sp
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; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]
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%arr3idx1 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 0
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store i32 1, i32* %arr3idx1, align 4
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; CHECK-DAG: ldr [[RC:r[0-9]+]], .LCPI7_4
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; CHECK-DAG: add [[RC]], sp
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; CHECK-DAG: str [[REG]], [{{r[0-9]+}}]
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%arr3idx2 = getelementptr inbounds [224 x i32], [224 x i32]* %arr3, i32 0, i32 32
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store i32 1, i32* %arr3idx2, align 4
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ret void
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}
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