1
0
mirror of https://github.com/RPCS3/llvm-mirror.git synced 2024-10-30 15:32:52 +01:00
llvm-mirror/test/CodeGen/X86/vec_shuffle-14.ll
Stephen Lin 7e501cf4c3 Mass update to CodeGen tests to use CHECK-LABEL for labels corresponding to function definitions for more informative error messages. No functionality change and all updated tests passed locally.
This update was done with the following bash script:

  find test/CodeGen -name "*.ll" | \
  while read NAME; do
    echo "$NAME"
    if ! grep -q "^; *RUN: *llc.*debug" $NAME; then
      TEMP=`mktemp -t temp`
      cp $NAME $TEMP
      sed -n "s/^define [^@]*@\([A-Za-z0-9_]*\)(.*$/\1/p" < $NAME | \
      while read FUNC; do
        sed -i '' "s/;\(.*\)\([A-Za-z0-9_-]*\):\( *\)$FUNC: *\$/;\1\2-LABEL:\3$FUNC:/g" $TEMP
      done
      sed -i '' "s/;\(.*\)-LABEL-LABEL:/;\1-LABEL:/" $TEMP
      sed -i '' "s/;\(.*\)-NEXT-LABEL:/;\1-NEXT:/" $TEMP
      sed -i '' "s/;\(.*\)-NOT-LABEL:/;\1-NOT:/" $TEMP
      sed -i '' "s/;\(.*\)-DAG-LABEL:/;\1-DAG:/" $TEMP
      mv $TEMP $NAME
    fi
  done

llvm-svn: 186280
2013-07-14 06:24:09 +00:00

71 lines
2.1 KiB
LLVM

; RUN: llc < %s -march=x86 -mattr=+sse2 | FileCheck %s -check-prefix=X86-32
; RUN: llc < %s -march=x86-64 -mattr=+sse2 | FileCheck %s -check-prefix=X86-64
define <4 x i32> @t1(i32 %a) nounwind {
entry:
%tmp = insertelement <4 x i32> undef, i32 %a, i32 0
%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp, <4 x i32> < i32 4, i32 1, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp6
; X86-32-LABEL: t1:
; X86-32: movd 4(%esp), %xmm0
; X86-64-LABEL: t1:
; X86-64: movd %e{{..}}, %xmm0
}
define <2 x i64> @t2(i64 %a) nounwind {
entry:
%tmp = insertelement <2 x i64> undef, i64 %a, i32 0
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %tmp, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
; X86-32-LABEL: t2:
; X86-32: movq 4(%esp), %xmm0
; X86-64-LABEL: t2:
; X86-64: movd %r{{..}}, %xmm0
}
define <2 x i64> @t3(<2 x i64>* %a) nounwind {
entry:
%tmp4 = load <2 x i64>* %a, align 16 ; <<2 x i64>> [#uses=1]
%tmp6 = bitcast <2 x i64> %tmp4 to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp7 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp6, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
%tmp8 = bitcast <4 x i32> %tmp7 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp8
; X86-32-LABEL: t3:
; X86-32: movl 4(%esp)
; X86-32: movq
; X86-64-LABEL: t3:
; X86-64: movq ({{.*}}), %xmm0
}
define <2 x i64> @t4(<2 x i64> %a) nounwind {
entry:
%tmp5 = bitcast <2 x i64> %a to <4 x i32> ; <<4 x i32>> [#uses=1]
%tmp6 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %tmp5, <4 x i32> < i32 4, i32 5, i32 2, i32 3 > ; <<4 x i32>> [#uses=1]
%tmp7 = bitcast <4 x i32> %tmp6 to <2 x i64> ; <<2 x i64>> [#uses=1]
ret <2 x i64> %tmp7
; X86-32-LABEL: t4:
; X86-32: movq %xmm0, %xmm0
; X86-64-LABEL: t4:
; X86-64: movq {{.*}}, %xmm0
}
define <2 x i64> @t5(<2 x i64> %a) nounwind {
entry:
%tmp6 = shufflevector <2 x i64> zeroinitializer, <2 x i64> %a, <2 x i32> < i32 2, i32 1 > ; <<4 x i32>> [#uses=1]
ret <2 x i64> %tmp6
; X86-32-LABEL: t5:
; X86-32: movq %xmm0, %xmm0
; X86-64-LABEL: t5:
; X86-64: movq {{.*}}, %xmm0
}