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a64d960eda
The SystemZ port currently relies on the order of the instruction operands
matching the order of the instruction field lists. This isn't desirable
for disassembly, where the two are matched only by name. E.g. the R1 and R2
fields of an RR instruction should have corresponding R1 and R2 operands.
The main complication is that addresses are compound operands,
and as far as I know there is no mechanism to allow individual
suboperands to be selected by name in "let Inst{...} = ..." assignments.
Luckily it doesn't really matter though. The SystemZ instruction
encoding groups all address fields together in a predictable order,
so it's just as valid to see the entire compound address operand as
a single field. That's the approach taken in this patch.
Matching by name in turn means that the operands to COPY SIGN and
CONVERT TO FIXED instructions can be given in natural order.
(It was easier to do this at the same time as the rename,
since otherwise the intermediate step was too confusing.)
No functional change intended.
llvm-svn: 181769
184 lines
7.5 KiB
C++
184 lines
7.5 KiB
C++
//===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the SystemZMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#define DEBUG_TYPE "mccodeemitter"
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#include "MCTargetDesc/SystemZMCTargetDesc.h"
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#include "MCTargetDesc/SystemZMCFixups.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstrInfo.h"
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using namespace llvm;
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namespace {
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class SystemZMCCodeEmitter : public MCCodeEmitter {
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const MCInstrInfo &MCII;
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MCContext &Ctx;
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public:
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SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
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: MCII(mcii), Ctx(ctx) {
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}
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~SystemZMCCodeEmitter() {}
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// OVerride MCCodeEmitter.
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virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const
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LLVM_OVERRIDE;
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private:
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// Automatically generated by TableGen.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// Called by the TableGen code to get the binary encoding of operand
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// MO in MI. Fixups is the list of fixups against MI.
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uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// Called by the TableGen code to get the binary encoding of an address.
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// The index, if any, is encoded first, followed by the base,
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// followed by the displacement. In a 20-bit displacement,
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// the low 12 bits are encoded before the high 8 bits.
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uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const;
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// Operand OpNum of MI needs a PC-relative fixup of kind Kind at
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// Offset bytes from the start of MI. Add the fixup to Fixups
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// and return the in-place addend, which since we're a RELA target
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// is always 0.
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uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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unsigned Kind, int64_t Offset) const;
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uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
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}
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uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
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}
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uint64_t getPLT16DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT16DBL, 2);
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}
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uint64_t getPLT32DBLEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PLT32DBL, 2);
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}
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};
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}
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MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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const MCSubtargetInfo &MCSTI,
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MCContext &Ctx) {
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return new SystemZMCCodeEmitter(MCII, Ctx);
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}
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void SystemZMCCodeEmitter::
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EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
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unsigned Size = MCII.get(MI.getOpcode()).getSize();
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// Big-endian insertion of Size bytes.
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unsigned ShiftValue = (Size * 8) - 8;
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for (unsigned I = 0; I != Size; ++I) {
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OS << uint8_t(Bits >> ShiftValue);
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ShiftValue -= 8;
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}
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}
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uint64_t SystemZMCCodeEmitter::
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getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo().getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<uint64_t>(MO.getImm());
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llvm_unreachable("Unexpected operand type!");
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}
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uint64_t SystemZMCCodeEmitter::
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getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
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uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
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assert(isUInt<4>(Base) && isUInt<12>(Disp));
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return (Base << 12) | Disp;
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}
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uint64_t SystemZMCCodeEmitter::
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getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
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uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
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assert(isUInt<4>(Base) && isInt<20>(Disp));
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return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
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}
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uint64_t SystemZMCCodeEmitter::
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getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
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uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
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uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
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assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
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return (Index << 16) | (Base << 12) | Disp;
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}
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uint64_t SystemZMCCodeEmitter::
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getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
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uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
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uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
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assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
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return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
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| ((Disp & 0xff000) >> 12);
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}
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uint64_t
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SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
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SmallVectorImpl<MCFixup> &Fixups,
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unsigned Kind, int64_t Offset) const {
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const MCOperand &MO = MI.getOperand(OpNum);
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// For compatibility with the GNU assembler, treat constant operands as
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// unadjusted PC-relative offsets.
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if (MO.isImm())
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return MO.getImm() / 2;
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const MCExpr *Expr = MO.getExpr();
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if (Offset) {
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// The operand value is relative to the start of MI, but the fixup
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// is relative to the operand field itself, which is Offset bytes
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// into MI. Add Offset to the relocation value to cancel out
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// this difference.
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const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
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Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
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}
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Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
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return 0;
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}
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#include "SystemZGenMCCodeEmitter.inc"
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