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cb60eaba94
This is a resubmit of r182877, which was reverted because it broken MCJIT tests on ARM. The patch leaves MCJIT on ARM as it was before: only enabled for iOS. I've CC'ed people from the original review and revert. FastISel was only enabled for iOS ARM and Thumb2, this patch enables it for ARM (not Thumb2) on Linux and NaCl, but not MCJIT. Thumb2 support needs a bit more work, mainly around register class restrictions. The patch punts to SelectionDAG when doing TLS relocation on non-Darwin targets. I will fix this and other FastISel-to-SelectionDAG failures in a separate patch. The patch also forces FastISel to retain frame pointers: iOS always keeps them for backtracking (so emitted code won't change because of this), but Linux was getting much worse code that was incorrect when using big frames (such as test-suite's lencod). I'll also fix this in a later patch, it will probably require a peephole so that FastISel doesn't rematerialize frame pointers back-to-back. The test changes are straightforward, similar to: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130513/174279.html They also add a vararg test that got dropped in that change. I ran all of lnt test-suite on A15 hardware with --optimize-option=-O0 and all the tests pass. All the tests also pass on x86 make check-all. I also re-ran the check-all tests that failed on ARM, and they all seem to pass. llvm-svn: 183966
118 lines
2.5 KiB
LLVM
118 lines
2.5 KiB
LLVM
; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-apple-ios | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=armv7-linux-gnueabi | FileCheck %s --check-prefix=ARM
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; RUN: llc < %s -O0 -fast-isel-abort -relocation-model=dynamic-no-pic -mtriple=thumbv7-apple-ios | FileCheck %s --check-prefix=THUMB
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; Test add with non-legal types
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define void @add_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: add_i1
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; THUMB: add_i1
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%a.addr = alloca i1, align 4
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%0 = add i1 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @add_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: add_i8
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; THUMB: add_i8
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%a.addr = alloca i8, align 4
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%0 = add i8 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @add_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: add_i16
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; THUMB: add_i16
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%a.addr = alloca i16, align 4
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%0 = add i16 %a, %b
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; ARM: add r0, r0, r1
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; THUMB: add r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test or with non-legal types
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define void @or_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: or_i1
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; THUMB: or_i1
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%a.addr = alloca i1, align 4
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%0 = or i1 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @or_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: or_i8
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; THUMB: or_i8
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%a.addr = alloca i8, align 4
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%0 = or i8 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @or_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: or_i16
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; THUMB: or_i16
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%a.addr = alloca i16, align 4
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%0 = or i16 %a, %b
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; ARM: orr r0, r0, r1
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; THUMB: orrs r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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; Test sub with non-legal types
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define void @sub_i1(i1 %a, i1 %b) nounwind ssp {
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entry:
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; ARM: sub_i1
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; THUMB: sub_i1
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%a.addr = alloca i1, align 4
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%0 = sub i1 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i1 %0, i1* %a.addr, align 4
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ret void
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}
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define void @sub_i8(i8 %a, i8 %b) nounwind ssp {
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entry:
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; ARM: sub_i8
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; THUMB: sub_i8
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%a.addr = alloca i8, align 4
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%0 = sub i8 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i8 %0, i8* %a.addr, align 4
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ret void
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}
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define void @sub_i16(i16 %a, i16 %b) nounwind ssp {
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entry:
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; ARM: sub_i16
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; THUMB: sub_i16
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%a.addr = alloca i16, align 4
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%0 = sub i16 %a, %b
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; ARM: sub r0, r0, r1
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; THUMB: subs r0, r0, r1
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store i16 %0, i16* %a.addr, align 4
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ret void
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}
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