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73624b6ac4
This enables targets to adapt their pass pipeline to the register allocator in use. For example, with the AArch64 backend, using PBQP with the cortex-a57, the FPLoadBalancing pass is no longer necessary. llvm-svn: 220321
15 lines
322 B
LLVM
15 lines
322 B
LLVM
; RUN: llc -mtriple=aarch64-linux-gnu -mcpu=cortex-a57 -regalloc=pbqp -pbqp-coalescing -o - %s | FileCheck %s
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define i32 @foo(i32 %a) {
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; CHECK-LABEL: foo:
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; CHECK: bl bar
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; CHECK: bl baz
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%call = call i32 @bar(i32 %a)
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%call1 = call i32 @baz(i32 %call)
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ret i32 %call1
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}
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declare i32 @bar(i32)
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declare i32 @baz(i32)
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