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The DAGCombiner tries to SimplifySelectCC as follows: select_cc(x, y, 16, 0, cc) -> shl(zext(set_cc(x, y, cc)), 4) It can't cope with the situation of reordered operands: select_cc(x, y, 0, 16, cc) In that case we just need to swap the operands and invert the Condition Code: select_cc(x, y, 16, 0, ~cc) Differential Revision: https://reviews.llvm.org/D53236 llvm-svn: 346484
55 lines
1.4 KiB
LLVM
55 lines
1.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=aarch64 | FileCheck %s
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define i64 @select_ogt_float(float %a, float %b) {
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; CHECK-LABEL: select_ogt_float:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: lsl x0, x8, #2
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; CHECK-NEXT: ret
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entry:
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%cc = fcmp ogt float %a, %b
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%sel = select i1 %cc, i64 4, i64 0
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ret i64 %sel
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}
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define i64 @select_ule_float_inverse(float %a, float %b) {
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; CHECK-LABEL: select_ule_float_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: fcmp s0, s1
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; CHECK-NEXT: cset w8, gt
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; CHECK-NEXT: lsl x0, x8, #2
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; CHECK-NEXT: ret
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entry:
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%cc = fcmp ule float %a, %b
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%sel = select i1 %cc, i64 0, i64 4
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ret i64 %sel
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}
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define i64 @select_eq_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: select_eq_i32:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: lsl x0, x8, #2
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; CHECK-NEXT: ret
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entry:
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%cc = icmp eq i32 %a, %b
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%sel = select i1 %cc, i64 4, i64 0
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ret i64 %sel
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}
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define i64 @select_ne_i32_inverse(i32 %a, i32 %b) {
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; CHECK-LABEL: select_ne_i32_inverse:
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; CHECK: // %bb.0: // %entry
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; CHECK-NEXT: cmp w0, w1
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; CHECK-NEXT: cset w8, eq
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; CHECK-NEXT: lsl x0, x8, #2
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; CHECK-NEXT: ret
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entry:
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%cc = icmp ne i32 %a, %b
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%sel = select i1 %cc, i64 0, i64 4
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ret i64 %sel
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}
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