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5f32a8dbc4
Currently a vector move of 0 or -1 will use different instructions depending on the size of the vector. Using a single instruction (the 128-bit one) for both gives more opportunity for Machine CSE to eliminate instructions. Differential Revision: https://reviews.llvm.org/D53579 llvm-svn: 345270
97 lines
3.1 KiB
LLVM
97 lines
3.1 KiB
LLVM
; Check that debug intrinsics do not affect code generation.
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; RUN: llc < %s -mtriple=aarch64-unknown-unknown -mattr=+avx | FileCheck --check-prefix=AARCH64-CHECK %s
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define i64 @simulate(<2 x i32> %a) {
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entry:
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%rand = tail call i64 @lrand48()
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulate:
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; AARCH64-CHECK: movi v0.2d, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB0_1:
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define i64 @simulateWithDebugIntrinsic(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.value(metadata i64 %rand, i64 0, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulateWithDebugIntrinsic
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; AARCH64-CHECK: movi v0.2d, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB1_1:
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define i64 @simulateWithDbgDeclare(<2 x i32> %a) local_unnamed_addr {
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entry:
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%rand = tail call i64 @lrand48() #3
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tail call void @llvm.dbg.declare(metadata i64 %rand, metadata !6, metadata !7), !dbg !8
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br label %body
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body: ; preds = %body, %entry
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%0 = phi <2 x i32> [ %add, %body ], [ zeroinitializer, %entry ]
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%add = add <2 x i32> %0, %a
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%rand1 = tail call i64 @lrand48() #3
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%cmp = icmp eq i64 %rand1, 0
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br i1 %cmp, label %end, label %body
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end: ; preds = %body
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%c = bitcast <2 x i32> %add to i64
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%res = add i64 %rand, %c
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ret i64 %res
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}
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; AARCH64-CHECK: simulateWithDbgDeclare:
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; AARCH64-CHECK: movi v0.2d, #0000000000000000
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; AARCH64-CHECK: bl lrand48
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; AARCH64-CHECK: mov x19, x0
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; AARCH64-CHECK: BB2_1:
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declare i64 @lrand48()
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declare void @llvm.dbg.value(metadata, i64, metadata, metadata)
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declare void @llvm.dbg.declare(metadata, metadata, metadata)
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!llvm.dbg.cu = !{!1}
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!llvm.module.flags = !{!3, !4}
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!1 = distinct !DICompileUnit(language: DW_LANG_C99, file: !2, runtimeVersion: 0, emissionKind: FullDebug)
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!2 = !DIFile(filename: "test.ll", directory: ".")
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!3 = !{i32 2, !"Dwarf Version", i32 4}
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!4 = !{i32 2, !"Debug Info Version", i32 3}
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!5 = distinct !DISubprogram(name: "simulateWithDebugIntrinsic", scope: !2, file: !2, line: 64, isLocal: false, isDefinition: true, scopeLine: 65, unit: !1)
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!6 = !DILocalVariable(name: "randv", scope: !5, file: !2, line: 69)
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!7 = !DIExpression()
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!8 = !DILocation(line: 132, column: 2, scope: !5)
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