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0cb285e7fd
Differentiate between word and subword memory operations as they take different amount of cycles to complete. This just adds a basic model of the subword latency to the scheduler. llvm-svn: 266898
30 lines
905 B
LLVM
30 lines
905 B
LLVM
; RUN: llc < %s -mtriple=lanai-unknown-unknown | FileCheck %s
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; Test scheduling of subwords.
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%struct.X = type { i16, i16 }
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define void @f(%struct.X* inreg nocapture %c) #0 {
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entry:
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%a = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 0
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%0 = load i16, i16* %a, align 2
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%inc = add i16 %0, 1
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store i16 %inc, i16* %a, align 2
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%b = getelementptr inbounds %struct.X, %struct.X* %c, i32 0, i32 1
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%1 = load i16, i16* %b, align 2
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%dec = add i16 %1, -1
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store i16 %dec, i16* %b, align 2
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ret void
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}
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; Verify that the two loads occur before the stores. Without memory
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; disambiguation and subword schedule, the resultant code was a per subword
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; load-modify-store sequence instead of the more optimal schedule where all
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; loads occurred before modification and storage.
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; CHECK: uld.h
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; CHECK-NEXT: uld.h
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; CHECK-NEXT: add
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; CHECK-NEXT: st.h
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; CHECK-NEXT: sub
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; CHECK-NEXT: st.h
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