Matt Arsenault ab7621bbc3 AMDGPU: Don't use the default cpu in a few tests ... Avoids unnecessary test changes in a future commit. llvm-svn: 357539		2019-04-03 00:00:58 +00:00
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expected-target-index-name.mir
intrinsics.mir
invalid-target-index-operand.mir
lit.local.cfg
machine-function-info-no-ir.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
machine-function-info-register-parse-error1.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
machine-function-info-register-parse-error2.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
machine-function-info.ll	AMDGPU: Don't use the default cpu in a few tests	2019-04-03 00:00:58 +00:00
mfi-frame-offset-reg-class.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-parse-error-frame-offset-reg.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-parse-error-scratch-rsrc-reg.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-parse-error-scratch-wave-offset-reg.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-parse-error-stack-ptr-offset-reg.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-scratch-rsrc-reg-reg-class.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-scratch-wave-offset-reg-class.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mfi-stack-ptr-offset-reg-class.mir	MIR: Allow targets to serialize MachineFunctionInfo	2019-03-14 22:54:43 +00:00
mir-canon-multi.mir
parse-order-reserved-regs.mir	MIR: Freeze reserved regs after parsing everything	2019-03-27 16:12:26 +00:00
stack-id.mir
syncscopes.mir
target-flags.mir
target-index-operands.mir