mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-20 11:33:24 +02:00
0149d0fb75
Summary: WebAssemblySubtarget.cpp expects a default 'generic' CPU to exist, and this seems to be prevalent with other targets. It makes sense to have something between MVP and bleeding-edge, even though for now it's the same as MVP. This removes a warning that's currently generated. Subscribers: jfb, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D11546 llvm-svn: 243345
66 lines
2.5 KiB
TableGen
66 lines
2.5 KiB
TableGen
//- WebAssembly.td - Describe the WebAssembly Target Machine --*- tablegen -*-//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
// This is a target description file for the WebAssembly architecture, which is
|
|
// also known as "wasm".
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target-independent interfaces which we are implementing
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "llvm/Target/Target.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// WebAssembly Subtarget features.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def FeatureSIMD128 : SubtargetFeature<"simd128", "HasSIMD128", "false",
|
|
"Enable 128-bit SIMD">;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Architectures.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Register File Description
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "WebAssemblyRegisterInfo.td"
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Instruction Descriptions
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
include "WebAssemblyInstrInfo.td"
|
|
|
|
def WebAssemblyInstrInfo : InstrInfo;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// WebAssembly Processors supported.
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
// Minimal Viable Product.
|
|
def : ProcessorModel<"mvp", NoSchedModel, []>;
|
|
|
|
// Generic processor: latest stable version.
|
|
def : ProcessorModel<"generic", NoSchedModel, []>;
|
|
|
|
// Latest and greatest experimental version of WebAssembly. Bugs included!
|
|
def : ProcessorModel<"bleeding-edge", NoSchedModel, [FeatureSIMD128]>;
|
|
|
|
//===----------------------------------------------------------------------===//
|
|
// Target Declaration
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
def WebAssembly : Target {
|
|
let InstructionSet = WebAssemblyInstrInfo;
|
|
}
|