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17a641437c
Summary: This code is based on AArch64 for modern backend good practice, and NVPTX for virtual ISA concerns. Reviewers: sunfish Subscribers: aemerson, llvm-commits, jfb Differential Revision: http://reviews.llvm.org/D11070 llvm-svn: 241923
55 lines
2.2 KiB
TableGen
55 lines
2.2 KiB
TableGen
//WebAssemblyRegisterInfo.td-Describe the WebAssembly Registers -*- tablegen -*-
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// \brief This file describes the WebAssembly register classes and some nominal
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/// physical registers.
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///
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//===----------------------------------------------------------------------===//
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class WebAssemblyReg<string n> : Register<n> {
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let Namespace = "WebAssembly";
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}
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class WebAssemblyRegClass<list<ValueType> regTypes, int alignment, dag regList>
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: RegisterClass<"WebAssembly", regTypes, alignment, regList>;
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//===----------------------------------------------------------------------===//
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// Registers
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//===----------------------------------------------------------------------===//
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// Special registers used as the frame and stack pointer.
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//
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// WebAssembly may someday supports mixed 32-bit and 64-bit heaps in the same
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// application, which requires separate width FP and SP.
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def FP32 : WebAssemblyReg<"%FP32">;
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def FP64 : WebAssemblyReg<"%FP64">;
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def SP32 : WebAssemblyReg<"%SP32">;
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def SP64 : WebAssemblyReg<"%SP64">;
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// TODO(jfb) The following comes from NVPTX. Is it really needed, or can we do
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// away with it? Try deleting once the backend works.
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// WebAssembly uses virtual registers, but the backend defines a few physical
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// registers here to keep SDAG and the MachineInstr layers happy.
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foreach i = 0-4 in {
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def I#i : WebAssemblyReg<"%i."#i>; // i32
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def L#i : WebAssemblyReg<"%l."#i>; // i64
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def F#i : WebAssemblyReg<"%f."#i>; // f32
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def D#i : WebAssemblyReg<"%d."#i>; // f64
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}
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//===----------------------------------------------------------------------===//
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// Register classes
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//===----------------------------------------------------------------------===//
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def Int32 : WebAssemblyRegClass<[i32], 32, (add (sequence "I%u", 0, 4), SP32)>;
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def Int64 : WebAssemblyRegClass<[i64], 64, (add (sequence "L%u", 0, 4), SP64)>;
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def Float32 : WebAssemblyRegClass<[f32], 32, (add (sequence "F%u", 0, 4))>;
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def Float64 : WebAssemblyRegClass<[f64], 64, (add (sequence "D%u", 0, 4))>;
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