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634 lines
24 KiB
C++
634 lines
24 KiB
C++
//===-- AlphaISelLowering.cpp - Alpha DAG Lowering Implementation ---------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by Andrew Lenharth and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AlphaISelLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "AlphaISelLowering.h"
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#include "AlphaTargetMachine.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/SelectionDAG.h"
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#include "llvm/CodeGen/SSARegMap.h"
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#include "llvm/Constants.h"
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#include "llvm/Function.h"
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#include "llvm/Module.h"
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#include "llvm/Support/CommandLine.h"
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#include <iostream>
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using namespace llvm;
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/// AddLiveIn - This helper function adds the specified physical register to the
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/// MachineFunction as a live in value. It also creates a corresponding virtual
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/// register for it.
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static unsigned AddLiveIn(MachineFunction &MF, unsigned PReg,
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TargetRegisterClass *RC) {
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assert(RC->contains(PReg) && "Not the correct regclass!");
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unsigned VReg = MF.getSSARegMap()->createVirtualRegister(RC);
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MF.addLiveIn(PReg, VReg);
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return VReg;
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}
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AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM) {
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// Set up the TargetLowering object.
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//I am having problems with shr n ubyte 1
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setShiftAmountType(MVT::i64);
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setSetCCResultType(MVT::i64);
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setSetCCResultContents(ZeroOrOneSetCCResult);
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addRegisterClass(MVT::i64, Alpha::GPRCRegisterClass);
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addRegisterClass(MVT::f64, Alpha::F8RCRegisterClass);
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addRegisterClass(MVT::f32, Alpha::F4RCRegisterClass);
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setOperationAction(ISD::BRIND, MVT::i64, Expand);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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setOperationAction(ISD::SELECT_CC, MVT::Other, Expand);
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setOperationAction(ISD::EXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
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setOperationAction(ISD::ZEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::ZEXTLOAD, MVT::i32, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i1, Promote);
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setOperationAction(ISD::SEXTLOAD, MVT::i8, Expand);
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setOperationAction(ISD::SEXTLOAD, MVT::i16, Expand);
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setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
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setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
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setOperationAction(ISD::FREM, MVT::f32, Expand);
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setOperationAction(ISD::FREM, MVT::f64, Expand);
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setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
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setOperationAction(ISD::SINT_TO_FP, MVT::i64, Custom);
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setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
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setOperationAction(ISD::FP_TO_SINT, MVT::i64, Custom);
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if (!TM.getSubtarget<AlphaSubtarget>().hasCT()) {
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setOperationAction(ISD::CTPOP , MVT::i64 , Expand);
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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setOperationAction(ISD::CTLZ , MVT::i64 , Expand);
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}
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setOperationAction(ISD::BSWAP , MVT::i64, Expand);
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setOperationAction(ISD::ROTL , MVT::i64, Expand);
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setOperationAction(ISD::ROTR , MVT::i64, Expand);
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setOperationAction(ISD::SREM , MVT::i64, Custom);
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setOperationAction(ISD::UREM , MVT::i64, Custom);
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setOperationAction(ISD::SDIV , MVT::i64, Custom);
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setOperationAction(ISD::UDIV , MVT::i64, Custom);
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setOperationAction(ISD::MEMMOVE , MVT::Other, Expand);
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setOperationAction(ISD::MEMSET , MVT::Other, Expand);
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setOperationAction(ISD::MEMCPY , MVT::Other, Expand);
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// We don't support sin/cos/sqrt
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setOperationAction(ISD::FSIN , MVT::f64, Expand);
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setOperationAction(ISD::FCOS , MVT::f64, Expand);
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setOperationAction(ISD::FSIN , MVT::f32, Expand);
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setOperationAction(ISD::FCOS , MVT::f32, Expand);
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setOperationAction(ISD::FSQRT, MVT::f64, Expand);
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setOperationAction(ISD::FSQRT, MVT::f32, Expand);
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setOperationAction(ISD::SETCC, MVT::f32, Promote);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
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// Not implemented yet.
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setOperationAction(ISD::STACKSAVE, MVT::Other, Expand);
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setOperationAction(ISD::STACKRESTORE, MVT::Other, Expand);
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setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
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// We want to legalize GlobalAddress and ConstantPool and
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// ExternalSymbols nodes into the appropriate instructions to
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// materialize the address.
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setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
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setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
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setOperationAction(ISD::ExternalSymbol, MVT::i64, Custom);
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setOperationAction(ISD::VASTART, MVT::Other, Custom);
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setOperationAction(ISD::VAEND, MVT::Other, Expand);
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setOperationAction(ISD::VACOPY, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::Other, Custom);
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setOperationAction(ISD::VAARG, MVT::i32, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setStackPointerRegisterToSaveRestore(Alpha::R30);
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setOperationAction(ISD::ConstantFP, MVT::f64, Expand);
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setOperationAction(ISD::ConstantFP, MVT::f32, Expand);
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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computeRegisterProperties();
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useITOF = TM.getSubtarget<AlphaSubtarget>().hasF2I();
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}
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const char *AlphaTargetLowering::getTargetNodeName(unsigned Opcode) const {
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switch (Opcode) {
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default: return 0;
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case AlphaISD::ITOFT_: return "Alpha::ITOFT_";
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case AlphaISD::FTOIT_: return "Alpha::FTOIT_";
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case AlphaISD::CVTQT_: return "Alpha::CVTQT_";
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case AlphaISD::CVTQS_: return "Alpha::CVTQS_";
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case AlphaISD::CVTTQ_: return "Alpha::CVTTQ_";
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case AlphaISD::GPRelHi: return "Alpha::GPRelHi";
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case AlphaISD::GPRelLo: return "Alpha::GPRelLo";
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case AlphaISD::RelLit: return "Alpha::RelLit";
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case AlphaISD::GlobalBaseReg: return "Alpha::GlobalBaseReg";
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case AlphaISD::GlobalRetAddr: return "Alpha::GlobalRetAddr";
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case AlphaISD::CALL: return "Alpha::CALL";
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case AlphaISD::DivCall: return "Alpha::DivCall";
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case AlphaISD::RET_FLAG: return "Alpha::RET_FLAG";
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}
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}
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//http://www.cs.arizona.edu/computer.help/policy/DIGITAL_unix/AA-PY8AC-TET1_html/callCH3.html#BLOCK21
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//For now, just use variable size stack frame format
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//In a standard call, the first six items are passed in registers $16
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//- $21 and/or registers $f16 - $f21. (See Section 4.1.2 for details
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//of argument-to-register correspondence.) The remaining items are
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//collected in a memory argument list that is a naturally aligned
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//array of quadwords. In a standard call, this list, if present, must
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//be passed at 0(SP).
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//7 ... n 0(SP) ... (n-7)*8(SP)
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// //#define FP $15
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// //#define RA $26
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// //#define PV $27
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// //#define GP $29
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// //#define SP $30
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static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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int &VarArgsBase,
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int &VarArgsOffset,
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unsigned int &GP,
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unsigned int &RA) {
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MachineFunction &MF = DAG.getMachineFunction();
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MachineFrameInfo *MFI = MF.getFrameInfo();
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SSARegMap *RegMap = MF.getSSARegMap();
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std::vector<SDOperand> ArgValues;
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SDOperand Root = Op.getOperand(0);
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GP = AddLiveIn(MF, Alpha::R29, &Alpha::GPRCRegClass);
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RA = AddLiveIn(MF, Alpha::R26, &Alpha::GPRCRegClass);
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unsigned args_int[] = {
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Alpha::R16, Alpha::R17, Alpha::R18, Alpha::R19, Alpha::R20, Alpha::R21};
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unsigned args_float[] = {
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Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
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for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
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SDOperand argt;
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MVT::ValueType ObjectVT = Op.getValue(ArgNo).getValueType();
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SDOperand ArgVal;
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if (ArgNo < 6) {
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unsigned Vreg;
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switch (ObjectVT) {
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default:
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std::cerr << "Unknown Type " << ObjectVT << "\n";
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abort();
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case MVT::f64:
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args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
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&Alpha::F8RCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
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break;
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case MVT::f32:
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args_float[ArgNo] = AddLiveIn(MF, args_float[ArgNo],
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&Alpha::F4RCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_float[ArgNo], ObjectVT);
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break;
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case MVT::i64:
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args_int[ArgNo] = AddLiveIn(MF, args_int[ArgNo],
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&Alpha::GPRCRegClass);
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ArgVal = DAG.getCopyFromReg(Root, args_int[ArgNo], MVT::i64);
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break;
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}
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} else { //more args
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// Create the frame index object for this incoming parameter...
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int FI = MFI->CreateFixedObject(8, 8 * (ArgNo - 6));
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// Create the SelectionDAG nodes corresponding to a load
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//from this parameter
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SDOperand FIN = DAG.getFrameIndex(FI, MVT::i64);
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ArgVal = DAG.getLoad(ObjectVT, Root, FIN, DAG.getSrcValue(NULL));
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}
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ArgValues.push_back(ArgVal);
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}
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// If the functions takes variable number of arguments, copy all regs to stack
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bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
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if (isVarArg) {
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VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
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std::vector<SDOperand> LS;
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for (int i = 0; i < 6; ++i) {
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if (MRegisterInfo::isPhysicalRegister(args_int[i]))
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args_int[i] = AddLiveIn(MF, args_int[i], &Alpha::GPRCRegClass);
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SDOperand argt = DAG.getCopyFromReg(Root, args_int[i], MVT::i64);
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int FI = MFI->CreateFixedObject(8, -8 * (6 - i));
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if (i == 0) VarArgsBase = FI;
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SDOperand SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
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SDFI, DAG.getSrcValue(NULL)));
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if (MRegisterInfo::isPhysicalRegister(args_float[i]))
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args_float[i] = AddLiveIn(MF, args_float[i], &Alpha::F8RCRegClass);
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argt = DAG.getCopyFromReg(Root, args_float[i], MVT::f64);
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FI = MFI->CreateFixedObject(8, - 8 * (12 - i));
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SDFI = DAG.getFrameIndex(FI, MVT::i64);
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LS.push_back(DAG.getNode(ISD::STORE, MVT::Other, Root, argt,
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SDFI, DAG.getSrcValue(NULL)));
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}
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//Set up a token factor with all the stack traffic
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS);
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}
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ArgValues.push_back(Root);
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// Return the new list of results.
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std::vector<MVT::ValueType> RetVT(Op.Val->value_begin(),
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Op.Val->value_end());
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return DAG.getNode(ISD::MERGE_VALUES, RetVT, ArgValues);
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}
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static SDOperand LowerRET(SDOperand Op, SelectionDAG &DAG, unsigned int RA) {
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SDOperand Copy = DAG.getCopyToReg(Op.getOperand(0), Alpha::R26,
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DAG.getNode(AlphaISD::GlobalRetAddr, MVT::i64),
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SDOperand());
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switch (Op.getNumOperands()) {
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default:
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assert(0 && "Do not know how to return this many arguments!");
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abort();
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case 1:
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break;
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//return SDOperand(); // ret void is legal
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case 3: {
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MVT::ValueType ArgVT = Op.getOperand(1).getValueType();
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unsigned ArgReg;
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if (MVT::isInteger(ArgVT))
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ArgReg = Alpha::R0;
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else {
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assert(MVT::isFloatingPoint(ArgVT));
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ArgReg = Alpha::F0;
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}
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Copy = DAG.getCopyToReg(Copy, ArgReg, Op.getOperand(1), Copy.getValue(1));
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if(DAG.getMachineFunction().liveout_empty())
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DAG.getMachineFunction().addLiveOut(ArgReg);
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break;
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}
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}
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return DAG.getNode(AlphaISD::RET_FLAG, MVT::Other, Copy, Copy.getValue(1));
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}
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std::pair<SDOperand, SDOperand>
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AlphaTargetLowering::LowerCallTo(SDOperand Chain,
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const Type *RetTy, bool isVarArg,
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unsigned CallingConv, bool isTailCall,
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SDOperand Callee, ArgListTy &Args,
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SelectionDAG &DAG) {
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int NumBytes = 0;
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if (Args.size() > 6)
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NumBytes = (Args.size() - 6) * 8;
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Chain = DAG.getCALLSEQ_START(Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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std::vector<SDOperand> args_to_use;
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for (unsigned i = 0, e = Args.size(); i != e; ++i)
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{
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switch (getValueType(Args[i].second)) {
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default: assert(0 && "Unexpected ValueType for argument!");
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case MVT::i1:
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case MVT::i8:
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case MVT::i16:
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case MVT::i32:
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// Promote the integer to 64 bits. If the input type is signed use a
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// sign extend, otherwise use a zero extend.
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if (Args[i].second->isSigned())
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Args[i].first = DAG.getNode(ISD::SIGN_EXTEND, MVT::i64, Args[i].first);
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else
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Args[i].first = DAG.getNode(ISD::ZERO_EXTEND, MVT::i64, Args[i].first);
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break;
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case MVT::i64:
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case MVT::f64:
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case MVT::f32:
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break;
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}
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args_to_use.push_back(Args[i].first);
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}
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std::vector<MVT::ValueType> RetVals;
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MVT::ValueType RetTyVT = getValueType(RetTy);
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MVT::ValueType ActualRetTyVT = RetTyVT;
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if (RetTyVT >= MVT::i1 && RetTyVT <= MVT::i32)
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ActualRetTyVT = MVT::i64;
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if (RetTyVT != MVT::isVoid)
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RetVals.push_back(ActualRetTyVT);
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RetVals.push_back(MVT::Other);
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std::vector<SDOperand> Ops;
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Ops.push_back(Chain);
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Ops.push_back(Callee);
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Ops.insert(Ops.end(), args_to_use.begin(), args_to_use.end());
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SDOperand TheCall = DAG.getNode(AlphaISD::CALL, RetVals, Ops);
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Chain = TheCall.getValue(RetTyVT != MVT::isVoid);
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Chain = DAG.getNode(ISD::CALLSEQ_END, MVT::Other, Chain,
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DAG.getConstant(NumBytes, getPointerTy()));
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SDOperand RetVal = TheCall;
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if (RetTyVT != ActualRetTyVT) {
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RetVal = DAG.getNode(RetTy->isSigned() ? ISD::AssertSext : ISD::AssertZext,
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MVT::i64, RetVal, DAG.getValueType(RetTyVT));
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RetVal = DAG.getNode(ISD::TRUNCATE, RetTyVT, RetVal);
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}
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return std::make_pair(RetVal, Chain);
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}
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void AlphaTargetLowering::restoreGP(MachineBasicBlock* BB)
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{
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BuildMI(BB, Alpha::BIS, 2, Alpha::R29).addReg(GP).addReg(GP);
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}
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void AlphaTargetLowering::restoreRA(MachineBasicBlock* BB)
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{
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BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA);
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}
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static int getUID()
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{
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static int id = 0;
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return ++id;
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}
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/// LowerOperation - Provide custom lowering hooks for some operations.
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///
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SDOperand AlphaTargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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default: assert(0 && "Wasn't expecting to be able to lower this!");
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG,
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VarArgsBase,
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VarArgsOffset,
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GP, RA);
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case ISD::RET: return LowerRET(Op,DAG, getVRegRA());
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case ISD::SINT_TO_FP: {
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assert(MVT::i64 == Op.getOperand(0).getValueType() &&
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"Unhandled SINT_TO_FP type in custom expander!");
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SDOperand LD;
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bool isDouble = MVT::f64 == Op.getValueType();
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if (useITOF) {
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LD = DAG.getNode(AlphaISD::ITOFT_, MVT::f64, Op.getOperand(0));
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} else {
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int FrameIdx =
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DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
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SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
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SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
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Op.getOperand(0), FI, DAG.getSrcValue(0));
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LD = DAG.getLoad(MVT::f64, ST, FI, DAG.getSrcValue(0));
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}
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SDOperand FP = DAG.getNode(isDouble?AlphaISD::CVTQT_:AlphaISD::CVTQS_,
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isDouble?MVT::f64:MVT::f32, LD);
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return FP;
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}
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case ISD::FP_TO_SINT: {
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bool isDouble = MVT::f64 == Op.getOperand(0).getValueType();
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SDOperand src = Op.getOperand(0);
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if (!isDouble) //Promote
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src = DAG.getNode(ISD::FP_EXTEND, MVT::f64, src);
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src = DAG.getNode(AlphaISD::CVTTQ_, MVT::f64, src);
|
|
|
|
if (useITOF) {
|
|
return DAG.getNode(AlphaISD::FTOIT_, MVT::i64, src);
|
|
} else {
|
|
int FrameIdx =
|
|
DAG.getMachineFunction().getFrameInfo()->CreateStackObject(8, 8);
|
|
SDOperand FI = DAG.getFrameIndex(FrameIdx, MVT::i64);
|
|
SDOperand ST = DAG.getNode(ISD::STORE, MVT::Other, DAG.getEntryNode(),
|
|
src, FI, DAG.getSrcValue(0));
|
|
return DAG.getLoad(MVT::i64, ST, FI, DAG.getSrcValue(0));
|
|
}
|
|
}
|
|
case ISD::ConstantPool: {
|
|
ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
|
|
Constant *C = CP->get();
|
|
SDOperand CPI = DAG.getTargetConstantPool(C, MVT::i64, CP->getAlignment());
|
|
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, CPI,
|
|
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, CPI, Hi);
|
|
return Lo;
|
|
}
|
|
case ISD::GlobalAddress: {
|
|
GlobalAddressSDNode *GSDN = cast<GlobalAddressSDNode>(Op);
|
|
GlobalValue *GV = GSDN->getGlobal();
|
|
SDOperand GA = DAG.getTargetGlobalAddress(GV, MVT::i64, GSDN->getOffset());
|
|
|
|
// if (!GV->hasWeakLinkage() && !GV->isExternal() && !GV->hasLinkOnceLinkage()) {
|
|
if (GV->hasInternalLinkage()) {
|
|
SDOperand Hi = DAG.getNode(AlphaISD::GPRelHi, MVT::i64, GA,
|
|
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
SDOperand Lo = DAG.getNode(AlphaISD::GPRelLo, MVT::i64, GA, Hi);
|
|
return Lo;
|
|
} else
|
|
return DAG.getNode(AlphaISD::RelLit, MVT::i64, GA, DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
}
|
|
case ISD::ExternalSymbol: {
|
|
return DAG.getNode(AlphaISD::RelLit, MVT::i64,
|
|
DAG.getTargetExternalSymbol(cast<ExternalSymbolSDNode>(Op)->getSymbol(), MVT::i64),
|
|
DAG.getNode(AlphaISD::GlobalBaseReg, MVT::i64));
|
|
}
|
|
|
|
case ISD::UREM:
|
|
case ISD::SREM:
|
|
//Expand only on constant case
|
|
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
|
|
MVT::ValueType VT = Op.Val->getValueType(0);
|
|
unsigned Opc = Op.Val->getOpcode() == ISD::UREM ? ISD::UDIV : ISD::SDIV;
|
|
SDOperand Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
|
|
BuildUDIV(Op.Val, DAG, NULL) :
|
|
BuildSDIV(Op.Val, DAG, NULL);
|
|
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
|
|
Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
|
|
return Tmp1;
|
|
}
|
|
//fall through
|
|
case ISD::SDIV:
|
|
case ISD::UDIV:
|
|
if (MVT::isInteger(Op.getValueType())) {
|
|
if (Op.getOperand(1).getOpcode() == ISD::Constant)
|
|
return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
|
|
: BuildUDIV(Op.Val, DAG, NULL);
|
|
const char* opstr = 0;
|
|
switch(Op.getOpcode()) {
|
|
case ISD::UREM: opstr = "__remqu"; break;
|
|
case ISD::SREM: opstr = "__remq"; break;
|
|
case ISD::UDIV: opstr = "__divqu"; break;
|
|
case ISD::SDIV: opstr = "__divq"; break;
|
|
}
|
|
SDOperand Tmp1 = Op.getOperand(0),
|
|
Tmp2 = Op.getOperand(1),
|
|
Addr = DAG.getExternalSymbol(opstr, MVT::i64);
|
|
return DAG.getNode(AlphaISD::DivCall, MVT::i64, Addr, Tmp1, Tmp2);
|
|
}
|
|
break;
|
|
|
|
case ISD::VAARG: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand VAListP = Op.getOperand(1);
|
|
SDOperand VAListS = Op.getOperand(2);
|
|
|
|
SDOperand Base = DAG.getLoad(MVT::i64, Chain, VAListP, VAListS);
|
|
SDOperand Tmp = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
SDOperand Offset = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Base.getValue(1),
|
|
Tmp, DAG.getSrcValue(0), MVT::i32);
|
|
SDOperand DataPtr = DAG.getNode(ISD::ADD, MVT::i64, Base, Offset);
|
|
if (MVT::isFloatingPoint(Op.getValueType()))
|
|
{
|
|
//if fp && Offset < 6*8, then subtract 6*8 from DataPtr
|
|
SDOperand FPDataPtr = DAG.getNode(ISD::SUB, MVT::i64, DataPtr,
|
|
DAG.getConstant(8*6, MVT::i64));
|
|
SDOperand CC = DAG.getSetCC(MVT::i64, Offset,
|
|
DAG.getConstant(8*6, MVT::i64), ISD::SETLT);
|
|
DataPtr = DAG.getNode(ISD::SELECT, MVT::i64, CC, FPDataPtr, DataPtr);
|
|
}
|
|
|
|
SDOperand NewOffset = DAG.getNode(ISD::ADD, MVT::i64, Offset,
|
|
DAG.getConstant(8, MVT::i64));
|
|
SDOperand Update = DAG.getNode(ISD::TRUNCSTORE, MVT::Other,
|
|
Offset.getValue(1), NewOffset,
|
|
Tmp, DAG.getSrcValue(0),
|
|
DAG.getValueType(MVT::i32));
|
|
|
|
SDOperand Result;
|
|
if (Op.getValueType() == MVT::i32)
|
|
Result = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Update, DataPtr,
|
|
DAG.getSrcValue(0), MVT::i32);
|
|
else
|
|
Result = DAG.getLoad(Op.getValueType(), Update, DataPtr,
|
|
DAG.getSrcValue(0));
|
|
return Result;
|
|
}
|
|
case ISD::VACOPY: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand DestP = Op.getOperand(1);
|
|
SDOperand SrcP = Op.getOperand(2);
|
|
SDOperand DestS = Op.getOperand(3);
|
|
SDOperand SrcS = Op.getOperand(4);
|
|
|
|
SDOperand Val = DAG.getLoad(getPointerTy(), Chain, SrcP, SrcS);
|
|
SDOperand Result = DAG.getNode(ISD::STORE, MVT::Other, Val.getValue(1), Val,
|
|
DestP, DestS);
|
|
SDOperand NP = DAG.getNode(ISD::ADD, MVT::i64, SrcP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
Val = DAG.getExtLoad(ISD::SEXTLOAD, MVT::i64, Result, NP,
|
|
DAG.getSrcValue(0), MVT::i32);
|
|
SDOperand NPD = DAG.getNode(ISD::ADD, MVT::i64, DestP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, Val.getValue(1),
|
|
Val, NPD, DAG.getSrcValue(0),DAG.getValueType(MVT::i32));
|
|
}
|
|
case ISD::VASTART: {
|
|
SDOperand Chain = Op.getOperand(0);
|
|
SDOperand VAListP = Op.getOperand(1);
|
|
SDOperand VAListS = Op.getOperand(2);
|
|
|
|
// vastart stores the address of the VarArgsBase and VarArgsOffset
|
|
SDOperand FR = DAG.getFrameIndex(VarArgsBase, MVT::i64);
|
|
SDOperand S1 = DAG.getNode(ISD::STORE, MVT::Other, Chain, FR, VAListP,
|
|
VAListS);
|
|
SDOperand SA2 = DAG.getNode(ISD::ADD, MVT::i64, VAListP,
|
|
DAG.getConstant(8, MVT::i64));
|
|
return DAG.getNode(ISD::TRUNCSTORE, MVT::Other, S1,
|
|
DAG.getConstant(VarArgsOffset, MVT::i64), SA2,
|
|
DAG.getSrcValue(0), DAG.getValueType(MVT::i32));
|
|
}
|
|
}
|
|
|
|
return SDOperand();
|
|
}
|
|
|
|
SDOperand AlphaTargetLowering::CustomPromoteOperation(SDOperand Op,
|
|
SelectionDAG &DAG) {
|
|
assert(Op.getValueType() == MVT::i32 &&
|
|
Op.getOpcode() == ISD::VAARG &&
|
|
"Unknown node to custom promote!");
|
|
|
|
// The code in LowerOperation already handles i32 vaarg
|
|
return LowerOperation(Op, DAG);
|
|
}
|
|
|
|
|
|
//Inline Asm
|
|
|
|
/// getConstraintType - Given a constraint letter, return the type of
|
|
/// constraint it is for this target.
|
|
AlphaTargetLowering::ConstraintType
|
|
AlphaTargetLowering::getConstraintType(char ConstraintLetter) const {
|
|
switch (ConstraintLetter) {
|
|
default: break;
|
|
case 'f':
|
|
case 'r':
|
|
return C_RegisterClass;
|
|
}
|
|
return TargetLowering::getConstraintType(ConstraintLetter);
|
|
}
|
|
|
|
std::vector<unsigned> AlphaTargetLowering::
|
|
getRegClassForInlineAsmConstraint(const std::string &Constraint,
|
|
MVT::ValueType VT) const {
|
|
if (Constraint.size() == 1) {
|
|
switch (Constraint[0]) {
|
|
default: break; // Unknown constriant letter
|
|
case 'f':
|
|
return make_vector<unsigned>(Alpha::F0 , Alpha::F1 , Alpha::F2 ,
|
|
Alpha::F3 , Alpha::F4 , Alpha::F5 ,
|
|
Alpha::F6 , Alpha::F7 , Alpha::F8 ,
|
|
Alpha::F9 , Alpha::F10, Alpha::F11,
|
|
Alpha::F12, Alpha::F13, Alpha::F14,
|
|
Alpha::F15, Alpha::F16, Alpha::F17,
|
|
Alpha::F18, Alpha::F19, Alpha::F20,
|
|
Alpha::F21, Alpha::F22, Alpha::F23,
|
|
Alpha::F24, Alpha::F25, Alpha::F26,
|
|
Alpha::F27, Alpha::F28, Alpha::F29,
|
|
Alpha::F30, Alpha::F31, 0);
|
|
case 'r':
|
|
return make_vector<unsigned>(Alpha::R0 , Alpha::R1 , Alpha::R2 ,
|
|
Alpha::R3 , Alpha::R4 , Alpha::R5 ,
|
|
Alpha::R6 , Alpha::R7 , Alpha::R8 ,
|
|
Alpha::R9 , Alpha::R10, Alpha::R11,
|
|
Alpha::R12, Alpha::R13, Alpha::R14,
|
|
Alpha::R15, Alpha::R16, Alpha::R17,
|
|
Alpha::R18, Alpha::R19, Alpha::R20,
|
|
Alpha::R21, Alpha::R22, Alpha::R23,
|
|
Alpha::R24, Alpha::R25, Alpha::R26,
|
|
Alpha::R27, Alpha::R28, Alpha::R29,
|
|
Alpha::R30, Alpha::R31, 0);
|
|
|
|
}
|
|
}
|
|
|
|
return std::vector<unsigned>();
|
|
}
|