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https://github.com/RPCS3/llvm-mirror.git
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dacbc9891d
This converts the ARM AsmParser to use the new assembly matcher error reporting mechanism, which allows errors to be reported for multiple instruction encodings when it is ambiguous which one the user intended to use. By itself this doesn't improve many error messages, because we don't have diagnostic text for most operand types, but as we add that then this will allow more of those diagnostic strings to be used when they are relevant. Differential revision: https://reviews.llvm.org/D31530 llvm-svn: 314779
290 lines
9.5 KiB
ArmAsm
290 lines
9.5 KiB
ArmAsm
@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s
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@ RUN: not llvm-mc -triple armv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s
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@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=-fullfp16,+neon -show-encoding < %s 2>&1 | FileCheck %s
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@ RUN: not llvm-mc -triple thumbv8a-none-eabi -mattr=+fullfp16,-neon -show-encoding < %s 2>&1 | FileCheck %s
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vadd.f16 d0, d1, d2
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vadd.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vsub.f16 d0, d1, d2
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vsub.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmul.f16 d0, d1, d2
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vmul.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmul.f16 d1, d2, d3[2]
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vmul.f16 q4, q5, d6[3]
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmla.f16 d0, d1, d2
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vmla.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmla.f16 d5, d6, d7[2]
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vmla.f16 q5, q6, d7[3]
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmls.f16 d0, d1, d2
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vmls.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmls.f16 d5, d6, d7[2]
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vmls.f16 q5, q6, d7[3]
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vfma.f16 d0, d1, d2
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vfma.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vfms.f16 d0, d1, d2
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vfms.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vceq.f16 d2, d3, d4
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vceq.f16 q2, q3, q4
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vceq.f16 d2, d3, #0
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vceq.f16 q2, q3, #0
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcge.f16 d2, d3, d4
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vcge.f16 q2, q3, q4
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcge.f16 d2, d3, #0
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vcge.f16 q2, q3, #0
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcgt.f16 d2, d3, d4
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vcgt.f16 q2, q3, q4
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcgt.f16 d2, d3, #0
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vcgt.f16 q2, q3, #0
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcle.f16 d2, d3, d4
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vcle.f16 q2, q3, q4
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcle.f16 d2, d3, #0
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vcle.f16 q2, q3, #0
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vclt.f16 d2, d3, d4
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vclt.f16 q2, q3, q4
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vclt.f16 d2, d3, #0
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vclt.f16 q2, q3, #0
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vacge.f16 d0, d1, d2
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vacge.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vacgt.f16 d0, d1, d2
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vacgt.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vacle.f16 d0, d1, d2
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vacle.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vaclt.f16 d0, d1, d2
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vaclt.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vabd.f16 d0, d1, d2
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vabd.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vabs.f16 d0, d1
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vabs.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmax.f16 d0, d1, d2
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vmax.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmin.f16 d0, d1, d2
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vmin.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vmaxnm.f16 d0, d1, d2
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vmaxnm.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vminnm.f16 d0, d1, d2
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vminnm.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vpadd.f16 d0, d1, d2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vpmax.f16 d0, d1, d2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vpmin.f16 d0, d1, d2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrecpe.f16 d0, d1
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vrecpe.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrecps.f16 d0, d1, d2
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vrecps.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrsqrte.f16 d0, d1
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vrsqrte.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrsqrts.f16 d0, d1, d2
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vrsqrts.f16 q0, q1, q2
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vneg.f16 d0, d1
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vneg.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvt.s16.f16 d0, d1
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vcvt.u16.f16 d0, d1
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vcvt.f16.s16 d0, d1
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vcvt.f16.u16 d0, d1
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vcvt.s16.f16 q0, q1
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vcvt.u16.f16 q0, q1
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vcvt.f16.s16 q0, q1
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vcvt.f16.u16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvta.s16.f16 d0, d1
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vcvta.s16.f16 q0, q1
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vcvta.u16.f16 d0, d1
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vcvta.u16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvtm.s16.f16 d0, d1
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vcvtm.s16.f16 q0, q1
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vcvtm.u16.f16 d0, d1
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vcvtm.u16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvtn.s16.f16 d0, d1
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vcvtn.s16.f16 q0, q1
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vcvtn.u16.f16 d0, d1
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vcvtn.u16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvtp.s16.f16 d0, d1
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vcvtp.s16.f16 q0, q1
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vcvtp.u16.f16 d0, d1
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vcvtp.u16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vcvt.s16.f16 d0, d1, #1
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vcvt.u16.f16 d0, d1, #2
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vcvt.f16.s16 d0, d1, #3
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vcvt.f16.u16 d0, d1, #4
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vcvt.s16.f16 q0, q1, #5
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vcvt.u16.f16 q0, q1, #6
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vcvt.f16.s16 q0, q1, #7
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vcvt.f16.u16 q0, q1, #8
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrinta.f16.f16 d0, d1
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vrinta.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrintm.f16.f16 d0, d1
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vrintm.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrintn.f16.f16 d0, d1
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vrintn.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrintp.f16.f16 d0, d1
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vrintp.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrintx.f16.f16 d0, d1
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vrintx.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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vrintz.f16.f16 d0, d1
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vrintz.f16.f16 q0, q1
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@ CHECK: instruction requires: {{full half-float|NEON}}
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@ CHECK: instruction requires: {{full half-float|NEON}}
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