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a1d7f2fdc1
Those two subtarget features were awkward because their semantics are reversed: each one indicates the _lack_ of support for something in the architecture, rather than the presence. As a consequence, you don't get the behavior you want if you combine two sets of feature bits. Each SubtargetFeature for an FP architecture version now comes in four versions, one for each combination of those options. So you can still say (for example) '+vfp2' in a feature string and it will mean what it's always meant, but there's a new string '+vfp2d16sp' meaning the version without those extra options. A lot of this change is just mechanically replacing positive checks for the old features with negative checks for the new ones. But one more interesting change is that I've rearranged getFPUFeatures() so that the main FPU feature is appended to the output list *before* rather than after the features derived from the Restriction field, so that -fp64 and -d32 can override defaults added by the main feature. Reviewers: dmgreen, samparker, SjoerdMeijer Subscribers: srhines, javed.absar, eraman, kristof.beyls, hiraditya, zzheng, Petar.Avramovic, cfe-commits, llvm-commits Tags: #clang, #llvm Differential Revision: https://reviews.llvm.org/D60691 llvm-svn: 361845
81 lines
3.0 KiB
ArmAsm
81 lines
3.0 KiB
ArmAsm
@ RUN: not llvm-mc -triple armv8 -mattr=-fp-armv8d16sp -show-encoding < %s 2>&1 | FileCheck %s
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vmaxnm.f32 s4, d5, q1
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@ CHECK: error: invalid instruction
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vmaxnm.f64.f64 s4, d5, q1
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@ CHECK: error: invalid instruction
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vmaxnmge.f64.f64 s4, d5, q1
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@ CHECK: error: instruction 'vmaxnm' is not predicable, but condition code specified
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vcvta.s32.f32 s1, s2
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@ CHECK: error: instruction requires: FPARMv8
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vcvtp.u32.f32 s1, d2
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@ CHECK: error: operand must be a register in range [d0, d31]
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vcvtp.f32.u32 d1, q2
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@ CHECK: error: invalid instruction
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vcvtplo.f32.u32 s1, s2
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@ CHECK: error: instruction 'vcvtp' is not predicable, but condition code specified
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vrinta.f64.f64 s3, d12
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@ CHECK: error: invalid instruction
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vrintn.f32 d3, q12
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [d0, d31]
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@ CHECK: note: operand must be a register in range [q0, q15]
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vrintz.f32 d3, q12
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@ CHECK: error: invalid instruction, any one of the following would fix this:
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@ CHECK: note: operand must be a register in range [d0, d31]
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@ CHECK: note: operand must be a register in range [q0, q15]
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vrintmge.f32.f32 d3, d4
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@ CHECK: error: instruction 'vrintm' is not predicable, but condition code specified
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aesd.8 q0, s1
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@ CHECK: error: operand must be a register in range [q0, q15]
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aese.8 s0, q1
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@ CHECK: error: operand must be a register in range [q0, q15]
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aesimc.8 s0, q1
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@ CHECK: error: operand must be a register in range [q0, q15]
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aesmc.8 q0, d1
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@ CHECK: error: operand must be a register in range [q0, q15]
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aesdge.8 q0, q1
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@ CHECK: error: instruction 'aesd' is not predicable, but condition code specified
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sha1h.32 d0, q1
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha1su1.32 q0, s1
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha256su0.32 s0, q1
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha1heq.32 q0, q1
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@ CHECK: error: instruction 'sha1h' is not predicable, but condition code specified
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sha1c.32 s0, d1, q2
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@ CHECK: error: invalid instruction
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sha1m.32 q0, s1, q2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha1p.32 s0, q1, q2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha1su0.32 d0, q1, q2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha256h.32 q0, s1, q2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha256h2.32 q0, q1, s2
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@ CHECK: error: operand must be a register in range [q0, q15]
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sha256su1.32 s0, d1, q2
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@ CHECK: error: invalid instruction
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sha256su1lt.32 q0, d1, q2
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@ CHECK: error: instruction 'sha256su1' is not predicable, but condition code specified
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vmull.p64 q0, s1, s3
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@ CHECK: error: invalid instruction
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vmull.p64 s1, d2, d3
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@ CHECK: error: operand must be a register in range [q0, q15]
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vmullge.p64 q0, d16, d17
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@ CHECK: error: instruction 'vmull' is not predicable, but condition code specified
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// These instructions are predicable in VFP but not in NEON
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vrintzeq.f32 d0, d1
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vrintxgt.f32 d0, d1
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@ CHECK: error: invalid operand for instruction
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@ CHECK: error: invalid operand for instruction
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