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a4356ce0e6
With subregister liveness enabled we can detect the case where only parts of a register are live in, this is expressed as a 32bit lanemask. The current code only keeps registers in the live-in list and therefore enumerated all subregisters affected by the lanemask. This turned out to be too conservative as the subregister may also cover additional parts of the lanemask which are not live. Expressing a given lanemask by enumerating a minimum set of subregisters is computationally expensive so the best solution is to simply change the live-in list to store the lanemasks as well. This will reduce memory usage for targets using subregister liveness and slightly increase it for other targets Differential Revision: http://reviews.llvm.org/D12442 llvm-svn: 247171
293 lines
9.1 KiB
C++
293 lines
9.1 KiB
C++
//===-- SystemZShortenInst.cpp - Instruction-shortening pass --------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This pass tries to replace instructions with shorter forms. For example,
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// IILF can be replaced with LLILL or LLILH if the constant fits and if the
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// other 32 bits of the GR64 destination are not live.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZTargetMachine.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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using namespace llvm;
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#define DEBUG_TYPE "systemz-shorten-inst"
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namespace {
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class SystemZShortenInst : public MachineFunctionPass {
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public:
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static char ID;
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SystemZShortenInst(const SystemZTargetMachine &tm);
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const char *getPassName() const override {
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return "SystemZ Instruction Shortening";
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}
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bool processBlock(MachineBasicBlock &MBB);
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bool runOnMachineFunction(MachineFunction &F) override;
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private:
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bool shortenIIF(MachineInstr &MI, unsigned *GPRMap, unsigned LiveOther,
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unsigned LLIxL, unsigned LLIxH);
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bool shortenOn0(MachineInstr &MI, unsigned Opcode);
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bool shortenOn01(MachineInstr &MI, unsigned Opcode);
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bool shortenOn001(MachineInstr &MI, unsigned Opcode);
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bool shortenFPConv(MachineInstr &MI, unsigned Opcode);
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const SystemZInstrInfo *TII;
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// LowGPRs[I] has bit N set if LLVM register I includes the low
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// word of GPR N. HighGPRs is the same for the high word.
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unsigned LowGPRs[SystemZ::NUM_TARGET_REGS];
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unsigned HighGPRs[SystemZ::NUM_TARGET_REGS];
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};
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char SystemZShortenInst::ID = 0;
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} // end anonymous namespace
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FunctionPass *llvm::createSystemZShortenInstPass(SystemZTargetMachine &TM) {
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return new SystemZShortenInst(TM);
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}
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SystemZShortenInst::SystemZShortenInst(const SystemZTargetMachine &tm)
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: MachineFunctionPass(ID), TII(nullptr), LowGPRs(), HighGPRs() {
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// Set up LowGPRs and HighGPRs.
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for (unsigned I = 0; I < 16; ++I) {
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LowGPRs[SystemZMC::GR32Regs[I]] |= 1 << I;
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LowGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
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HighGPRs[SystemZMC::GRH32Regs[I]] |= 1 << I;
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HighGPRs[SystemZMC::GR64Regs[I]] |= 1 << I;
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if (unsigned GR128 = SystemZMC::GR128Regs[I]) {
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LowGPRs[GR128] |= 3 << I;
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HighGPRs[GR128] |= 3 << I;
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}
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}
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}
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// MI loads one word of a GPR using an IIxF instruction and LLIxL and LLIxH
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// are the halfword immediate loads for the same word. Try to use one of them
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// instead of IIxF. If MI loads the high word, GPRMap[X] is the set of high
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// words referenced by LLVM register X while LiveOther is the mask of low
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// words that are currently live, and vice versa.
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bool SystemZShortenInst::shortenIIF(MachineInstr &MI, unsigned *GPRMap,
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unsigned LiveOther, unsigned LLIxL,
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unsigned LLIxH) {
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unsigned Reg = MI.getOperand(0).getReg();
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assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
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unsigned GPRs = GPRMap[Reg];
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assert(GPRs != 0 && "Register must be a GPR");
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if (GPRs & LiveOther)
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return false;
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uint64_t Imm = MI.getOperand(1).getImm();
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if (SystemZ::isImmLL(Imm)) {
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MI.setDesc(TII->get(LLIxL));
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MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
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return true;
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}
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if (SystemZ::isImmLH(Imm)) {
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MI.setDesc(TII->get(LLIxH));
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MI.getOperand(0).setReg(SystemZMC::getRegAsGR64(Reg));
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MI.getOperand(1).setImm(Imm >> 16);
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operand 0 has a 4-bit encoding.
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bool SystemZShortenInst::shortenOn0(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operands 0 and 1 have a
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// 4-bit encoding.
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bool SystemZShortenInst::shortenOn01(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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return true;
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}
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return false;
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}
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// Change MI's opcode to Opcode if register operands 0, 1 and 2 have a
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// 4-bit encoding and if operands 0 and 1 are tied.
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bool SystemZShortenInst::shortenOn001(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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MI.getOperand(1).getReg() == MI.getOperand(0).getReg() &&
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SystemZMC::getFirstReg(MI.getOperand(2).getReg()) < 16) {
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MI.setDesc(TII->get(Opcode));
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return true;
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}
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return false;
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}
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// MI is a vector-style conversion instruction with the operand order:
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// destination, source, exact-suppress, rounding-mode. If both registers
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// have a 4-bit encoding then change it to Opcode, which has operand order:
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// destination, rouding-mode, source, exact-suppress.
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bool SystemZShortenInst::shortenFPConv(MachineInstr &MI, unsigned Opcode) {
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if (SystemZMC::getFirstReg(MI.getOperand(0).getReg()) < 16 &&
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SystemZMC::getFirstReg(MI.getOperand(1).getReg()) < 16) {
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MachineOperand Dest(MI.getOperand(0));
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MachineOperand Src(MI.getOperand(1));
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MachineOperand Suppress(MI.getOperand(2));
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MachineOperand Mode(MI.getOperand(3));
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MI.RemoveOperand(3);
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MI.RemoveOperand(2);
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MI.RemoveOperand(1);
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MI.RemoveOperand(0);
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MI.setDesc(TII->get(Opcode));
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MachineInstrBuilder(*MI.getParent()->getParent(), &MI)
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.addOperand(Dest)
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.addOperand(Mode)
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.addOperand(Src)
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.addOperand(Suppress);
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return true;
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}
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return false;
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}
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// Process all instructions in MBB. Return true if something changed.
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bool SystemZShortenInst::processBlock(MachineBasicBlock &MBB) {
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bool Changed = false;
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// Work out which words are live on exit from the block.
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unsigned LiveLow = 0;
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unsigned LiveHigh = 0;
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for (auto SI = MBB.succ_begin(), SE = MBB.succ_end(); SI != SE; ++SI) {
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for (const auto &LI : (*SI)->liveins()) {
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unsigned Reg = LI.PhysReg;
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assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
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LiveLow |= LowGPRs[Reg];
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LiveHigh |= HighGPRs[Reg];
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}
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}
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// Iterate backwards through the block looking for instructions to change.
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for (auto MBBI = MBB.rbegin(), MBBE = MBB.rend(); MBBI != MBBE; ++MBBI) {
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MachineInstr &MI = *MBBI;
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switch (MI.getOpcode()) {
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case SystemZ::IILF:
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Changed |= shortenIIF(MI, LowGPRs, LiveHigh, SystemZ::LLILL,
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SystemZ::LLILH);
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break;
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case SystemZ::IIHF:
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Changed |= shortenIIF(MI, HighGPRs, LiveLow, SystemZ::LLIHL,
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SystemZ::LLIHH);
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break;
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case SystemZ::WFADB:
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Changed |= shortenOn001(MI, SystemZ::ADBR);
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break;
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case SystemZ::WFDDB:
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Changed |= shortenOn001(MI, SystemZ::DDBR);
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break;
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case SystemZ::WFIDB:
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Changed |= shortenFPConv(MI, SystemZ::FIDBRA);
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break;
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case SystemZ::WLDEB:
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Changed |= shortenOn01(MI, SystemZ::LDEBR);
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break;
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case SystemZ::WLEDB:
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Changed |= shortenFPConv(MI, SystemZ::LEDBRA);
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break;
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case SystemZ::WFMDB:
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Changed |= shortenOn001(MI, SystemZ::MDBR);
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break;
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case SystemZ::WFLCDB:
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Changed |= shortenOn01(MI, SystemZ::LCDBR);
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break;
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case SystemZ::WFLNDB:
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Changed |= shortenOn01(MI, SystemZ::LNDBR);
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break;
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case SystemZ::WFLPDB:
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Changed |= shortenOn01(MI, SystemZ::LPDBR);
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break;
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case SystemZ::WFSQDB:
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Changed |= shortenOn01(MI, SystemZ::SQDBR);
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break;
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case SystemZ::WFSDB:
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Changed |= shortenOn001(MI, SystemZ::SDBR);
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break;
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case SystemZ::WFCDB:
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Changed |= shortenOn01(MI, SystemZ::CDBR);
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break;
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case SystemZ::VL32:
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// For z13 we prefer LDE over LE to avoid partial register dependencies.
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Changed |= shortenOn0(MI, SystemZ::LDE32);
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break;
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case SystemZ::VST32:
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Changed |= shortenOn0(MI, SystemZ::STE);
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break;
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case SystemZ::VL64:
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Changed |= shortenOn0(MI, SystemZ::LD);
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break;
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case SystemZ::VST64:
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Changed |= shortenOn0(MI, SystemZ::STD);
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break;
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}
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unsigned UsedLow = 0;
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unsigned UsedHigh = 0;
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for (auto MOI = MI.operands_begin(), MOE = MI.operands_end();
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MOI != MOE; ++MOI) {
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MachineOperand &MO = *MOI;
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if (MO.isReg()) {
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if (unsigned Reg = MO.getReg()) {
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assert(Reg < SystemZ::NUM_TARGET_REGS && "Invalid register number");
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if (MO.isDef()) {
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LiveLow &= ~LowGPRs[Reg];
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LiveHigh &= ~HighGPRs[Reg];
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} else if (!MO.isUndef()) {
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UsedLow |= LowGPRs[Reg];
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UsedHigh |= HighGPRs[Reg];
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}
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}
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}
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}
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LiveLow |= UsedLow;
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LiveHigh |= UsedHigh;
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}
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return Changed;
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}
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bool SystemZShortenInst::runOnMachineFunction(MachineFunction &F) {
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TII = static_cast<const SystemZInstrInfo *>(F.getSubtarget().getInstrInfo());
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bool Changed = false;
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for (auto &MBB : F)
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Changed |= processBlock(MBB);
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return Changed;
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}
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