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252 lines
8.7 KiB
C++
252 lines
8.7 KiB
C++
//===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the NVPTX implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "NVPTX.h"
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#include "NVPTXInstrInfo.h"
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#include "NVPTXTargetMachine.h"
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#include "llvm/ADT/STLExtras.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/IR/Function.h"
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using namespace llvm;
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#define GET_INSTRINFO_CTOR_DTOR
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#include "NVPTXGenInstrInfo.inc"
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// Pin the vtable to this file.
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void NVPTXInstrInfo::anchor() {}
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NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
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void NVPTXInstrInfo::copyPhysReg(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL,
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unsigned DestReg, unsigned SrcReg, bool KillSrc) const {
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const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
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const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
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const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
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if (DestRC->getSize() != SrcRC->getSize())
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report_fatal_error("Copy one register into another with a different width");
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unsigned Op;
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if (DestRC == &NVPTX::Int1RegsRegClass) {
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Op = NVPTX::IMOV1rr;
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} else if (DestRC == &NVPTX::Int16RegsRegClass) {
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Op = NVPTX::IMOV16rr;
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} else if (DestRC == &NVPTX::Int32RegsRegClass) {
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Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
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: NVPTX::BITCONVERT_32_F2I);
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} else if (DestRC == &NVPTX::Int64RegsRegClass) {
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Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
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: NVPTX::BITCONVERT_64_F2I);
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} else if (DestRC == &NVPTX::Float32RegsRegClass) {
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Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
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: NVPTX::BITCONVERT_32_I2F);
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} else if (DestRC == &NVPTX::Float64RegsRegClass) {
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Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
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: NVPTX::BITCONVERT_64_I2F);
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} else {
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llvm_unreachable("Bad register copy");
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}
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BuildMI(MBB, I, DL, get(Op), DestReg)
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.addReg(SrcReg, getKillRegState(KillSrc));
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}
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bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
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unsigned &DestReg) const {
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// Look for the appropriate part of TSFlags
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bool isMove = false;
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unsigned TSFlags =
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(MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
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isMove = (TSFlags == 1);
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if (isMove) {
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MachineOperand dest = MI.getOperand(0);
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MachineOperand src = MI.getOperand(1);
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assert(dest.isReg() && "dest of a movrr is not a reg");
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assert(src.isReg() && "src of a movrr is not a reg");
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SrcReg = src.getReg();
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DestReg = dest.getReg();
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return true;
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}
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return false;
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}
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bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
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unsigned &AddrSpace) const {
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bool isLoad = false;
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unsigned TSFlags =
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(MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
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isLoad = (TSFlags == 1);
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if (isLoad)
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AddrSpace = getLdStCodeAddrSpace(MI);
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return isLoad;
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}
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bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
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unsigned &AddrSpace) const {
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bool isStore = false;
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unsigned TSFlags =
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(MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
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isStore = (TSFlags == 1);
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if (isStore)
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AddrSpace = getLdStCodeAddrSpace(MI);
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return isStore;
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}
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bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
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unsigned addrspace = 0;
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if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
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return false;
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if (isLoadInstr(*MI, addrspace))
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if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
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return false;
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if (isStoreInstr(*MI, addrspace))
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if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
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return false;
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return true;
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}
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/// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
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/// true if it cannot be understood (e.g. it's a switch dispatch or isn't
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/// implemented for a target). Upon success, this returns false and returns
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/// with the following information in various cases:
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///
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/// 1. If this block ends with no branches (it just falls through to its succ)
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/// just return false, leaving TBB/FBB null.
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/// 2. If this block ends with only an unconditional branch, it sets TBB to be
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/// the destination block.
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/// 3. If this block ends with an conditional branch and it falls through to
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/// an successor block, it sets TBB to be the branch destination block and a
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/// list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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/// 4. If this block ends with an conditional branch and an unconditional
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/// block, it returns the 'true' destination in TBB, the 'false' destination
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/// in FBB, and a list of operands that evaluate the condition. These
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/// operands can be passed to other TargetInstrInfo methods to create new
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/// branches.
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///
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/// Note that RemoveBranch and InsertBranch must be implemented to support
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/// cases where this method returns success.
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///
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bool NVPTXInstrInfo::AnalyzeBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
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SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
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// If the block has no terminators, it just falls into the block after it.
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
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return false;
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// Get the last instruction in the block.
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MachineInstr *LastInst = I;
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// If there is only one terminator instruction, process it.
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if (I == MBB.begin() || !isUnpredicatedTerminator(--I)) {
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if (LastInst->getOpcode() == NVPTX::GOTO) {
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TBB = LastInst->getOperand(0).getMBB();
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return false;
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} else if (LastInst->getOpcode() == NVPTX::CBranch) {
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// Block ends with fall-through condbranch.
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TBB = LastInst->getOperand(1).getMBB();
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Cond.push_back(LastInst->getOperand(0));
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return false;
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}
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// Otherwise, don't know what this is.
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return true;
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}
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// Get the instruction before it if it's a terminator.
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MachineInstr *SecondLastInst = I;
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// If there are three terminators, we don't know what sort of block this is.
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if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(--I))
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return true;
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// If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
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if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
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LastInst->getOpcode() == NVPTX::GOTO) {
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TBB = SecondLastInst->getOperand(1).getMBB();
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Cond.push_back(SecondLastInst->getOperand(0));
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FBB = LastInst->getOperand(0).getMBB();
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return false;
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}
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// If the block ends with two NVPTX:GOTOs, handle it. The second one is not
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// executed, so remove it.
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if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
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LastInst->getOpcode() == NVPTX::GOTO) {
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TBB = SecondLastInst->getOperand(0).getMBB();
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I = LastInst;
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if (AllowModify)
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I->eraseFromParent();
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return false;
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}
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// Otherwise, can't handle this.
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return true;
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}
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unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator I = MBB.end();
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if (I == MBB.begin())
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return 0;
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--I;
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if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
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return 0;
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// Remove the branch.
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I->eraseFromParent();
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I = MBB.end();
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if (I == MBB.begin())
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return 1;
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--I;
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if (I->getOpcode() != NVPTX::CBranch)
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return 1;
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// Remove the branch.
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I->eraseFromParent();
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return 2;
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}
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unsigned NVPTXInstrInfo::InsertBranch(
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MachineBasicBlock &MBB, MachineBasicBlock *TBB, MachineBasicBlock *FBB,
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ArrayRef<MachineOperand> Cond, DebugLoc DL) const {
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// Shouldn't be a fall through.
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assert(TBB && "InsertBranch must not be told to insert a fallthrough");
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assert((Cond.size() == 1 || Cond.size() == 0) &&
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"NVPTX branch conditions have two components!");
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// One-way branch.
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if (!FBB) {
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if (Cond.empty()) // Unconditional branch
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BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
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else // Conditional branch
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BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
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.addMBB(TBB);
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return 1;
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}
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// Two-way Conditional Branch.
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BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
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BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
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return 2;
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}
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