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https://github.com/RPCS3/llvm-mirror.git
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5569b3eb62
Summary: These instructions technically do read from memory, but the memory is considered to be out of bounds for normal load/store instructions. shader-db stats: SGPRS: 1416075 -> 1413323 (-0.19 %) VGPRS: 867413 -> 863935 (-0.40 %) Spilled SGPRs: 1409 -> 1354 (-3.90 %) Spilled VGPRs: 63 -> 63 (0.00 %) Private memory VGPRs: 880 -> 880 (0.00 %) Scratch size: 2648 -> 2632 (-0.60 %) dwords per thread Code Size: 37889052 -> 37897340 (0.02 %) bytes LDS: 2147 -> 2147 (0.00 %) blocks Max Waves: 279243 -> 280369 (0.40 %) Wait states: 0 -> 0 (0.00 %) Reviewers: nhaehnle, mareko, arsenm Subscribers: kzhuravl, wdng, yaxunl, tony-tye Differential Revision: https://reviews.llvm.org/D27593 llvm-svn: 289219
60 lines
2.7 KiB
LLVM
60 lines
2.7 KiB
LLVM
;RUN: llc < %s -march=amdgcn -mcpu=verde -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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;RUN: llc < %s -march=amdgcn -mcpu=kabini -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
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;RUN: llc < %s -march=amdgcn -mcpu=stoney -verify-machineinstrs | FileCheck --check-prefix=GCN --check-prefix=16BANK %s
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;RUN: llc < %s -march=amdgcn -mcpu=tonga -verify-machineinstrs | FileCheck --check-prefix=GCN %s
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;GCN-LABEL: {{^}}main:
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;GCN-NOT: s_wqm
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;GCN: s_mov_b32 m0
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;GCN-DAG: v_interp_mov_f32
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;GCN-DAG: v_interp_p1_f32
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;GCN-DAG: v_interp_p2_f32
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define amdgpu_ps void @main(<16 x i8> addrspace(2)* inreg, <16 x i8> addrspace(2)* inreg, <32 x i8> addrspace(2)* inreg, i32 inreg, <2 x i32>) {
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main_body:
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%5 = call float @llvm.SI.fs.constant(i32 0, i32 0, i32 %3)
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%6 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %3, <2 x i32> %4)
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%7 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %3, <2 x i32> %4)
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %5, float %6, float %7, float %7)
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ret void
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}
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; Thest that v_interp_p1 uses different source and destination registers
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; on 16 bank LDS chips.
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; 16BANK-LABEL: {{^}}v_interp_p1_bank16_bug:
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; 16BANK-NOT: v_interp_p1_f32 [[DST:v[0-9]+]], [[DST]]
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define amdgpu_ps void @v_interp_p1_bank16_bug([6 x <16 x i8>] addrspace(2)* byval, [17 x <16 x i8>] addrspace(2)* byval, [17 x <4 x i32>] addrspace(2)* byval, [34 x <8 x i32>] addrspace(2)* byval, float inreg, i32 inreg, <2 x i32>, <2 x i32>, <2 x i32>, <3 x i32>, <2 x i32>, <2 x i32>, <2 x i32>, float, float, float, float, float, float, i32, float, float) {
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main_body:
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%22 = call float @llvm.SI.fs.interp(i32 0, i32 0, i32 %5, <2 x i32> %7)
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%23 = call float @llvm.SI.fs.interp(i32 1, i32 0, i32 %5, <2 x i32> %7)
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%24 = call float @llvm.SI.fs.interp(i32 2, i32 0, i32 %5, <2 x i32> %7)
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%25 = call float @fabs(float %22)
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%26 = call float @fabs(float %23)
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%27 = call float @fabs(float %24)
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%28 = call i32 @llvm.SI.packf16(float %25, float %26)
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%29 = bitcast i32 %28 to float
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%30 = call i32 @llvm.SI.packf16(float %27, float 1.000000e+00)
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%31 = bitcast i32 %30 to float
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call void @llvm.SI.export(i32 15, i32 1, i32 1, i32 0, i32 1, float %29, float %31, float %29, float %31)
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ret void
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}
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; Function Attrs: readnone
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declare float @fabs(float) #1
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; Function Attrs: nounwind readnone
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declare i32 @llvm.SI.packf16(float, float) #0
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.fs.constant(i32, i32, i32) #0
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; Function Attrs: nounwind readnone
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declare float @llvm.SI.fs.interp(i32, i32, i32, <2 x i32>) #0
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declare void @llvm.SI.export(i32, i32, i32, i32, i32, float, float, float, float)
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attributes #0 = { nounwind readnone }
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attributes #1 = { readnone }
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