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https://github.com/RPCS3/llvm-mirror.git
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272 lines
8.2 KiB
LLVM
272 lines
8.2 KiB
LLVM
; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=knl | FileCheck %s
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; CHECK-LABEL: addpd512
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; CHECK: vaddpd
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; CHECK: ret
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define <8 x double> @addpd512(<8 x double> %y, <8 x double> %x) {
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entry:
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%add.i = fadd <8 x double> %x, %y
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ret <8 x double> %add.i
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}
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; CHECK-LABEL: addpd512fold
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; CHECK: vaddpd LCP{{.*}}(%rip)
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; CHECK: ret
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define <8 x double> @addpd512fold(<8 x double> %y) {
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entry:
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%add.i = fadd <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.800000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <8 x double> %add.i
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}
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; CHECK-LABEL: addps512
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; CHECK: vaddps
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; CHECK: ret
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define <16 x float> @addps512(<16 x float> %y, <16 x float> %x) {
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entry:
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%add.i = fadd <16 x float> %x, %y
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ret <16 x float> %add.i
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}
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; CHECK-LABEL: addps512fold
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; CHECK: vaddps LCP{{.*}}(%rip)
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; CHECK: ret
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define <16 x float> @addps512fold(<16 x float> %y) {
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entry:
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%add.i = fadd <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 4.500000e+00, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <16 x float> %add.i
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}
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; CHECK-LABEL: subpd512
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; CHECK: vsubpd
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; CHECK: ret
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define <8 x double> @subpd512(<8 x double> %y, <8 x double> %x) {
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entry:
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%sub.i = fsub <8 x double> %x, %y
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ret <8 x double> %sub.i
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}
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; CHECK-LABEL: @subpd512fold
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; CHECK: vsubpd (%
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; CHECK: ret
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define <8 x double> @subpd512fold(<8 x double> %y, <8 x double>* %x) {
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entry:
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%tmp2 = load <8 x double>* %x, align 8
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%sub.i = fsub <8 x double> %y, %tmp2
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ret <8 x double> %sub.i
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}
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; CHECK-LABEL: @subps512
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; CHECK: vsubps
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; CHECK: ret
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define <16 x float> @subps512(<16 x float> %y, <16 x float> %x) {
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entry:
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%sub.i = fsub <16 x float> %x, %y
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ret <16 x float> %sub.i
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}
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; CHECK-LABEL: subps512fold
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; CHECK: vsubps (%
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; CHECK: ret
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define <16 x float> @subps512fold(<16 x float> %y, <16 x float>* %x) {
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entry:
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%tmp2 = load <16 x float>* %x, align 4
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%sub.i = fsub <16 x float> %y, %tmp2
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ret <16 x float> %sub.i
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}
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; CHECK-LABEL: imulq512
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; CHECK: vpmuludq
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; CHECK: vpmuludq
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; CHECK: ret
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define <8 x i64> @imulq512(<8 x i64> %y, <8 x i64> %x) {
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%z = mul <8 x i64>%x, %y
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ret <8 x i64>%z
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}
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; CHECK-LABEL: mulpd512
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; CHECK: vmulpd
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; CHECK: ret
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define <8 x double> @mulpd512(<8 x double> %y, <8 x double> %x) {
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entry:
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%mul.i = fmul <8 x double> %x, %y
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ret <8 x double> %mul.i
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}
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; CHECK-LABEL: mulpd512fold
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; CHECK: vmulpd LCP{{.*}}(%rip)
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; CHECK: ret
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define <8 x double> @mulpd512fold(<8 x double> %y) {
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entry:
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%mul.i = fmul <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <8 x double> %mul.i
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}
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; CHECK-LABEL: mulps512
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; CHECK: vmulps
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; CHECK: ret
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define <16 x float> @mulps512(<16 x float> %y, <16 x float> %x) {
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entry:
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%mul.i = fmul <16 x float> %x, %y
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ret <16 x float> %mul.i
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}
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; CHECK-LABEL: mulps512fold
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; CHECK: vmulps LCP{{.*}}(%rip)
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; CHECK: ret
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define <16 x float> @mulps512fold(<16 x float> %y) {
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entry:
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%mul.i = fmul <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <16 x float> %mul.i
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}
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; CHECK-LABEL: divpd512
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; CHECK: vdivpd
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; CHECK: ret
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define <8 x double> @divpd512(<8 x double> %y, <8 x double> %x) {
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entry:
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%div.i = fdiv <8 x double> %x, %y
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ret <8 x double> %div.i
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}
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; CHECK-LABEL: divpd512fold
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; CHECK: vdivpd LCP{{.*}}(%rip)
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; CHECK: ret
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define <8 x double> @divpd512fold(<8 x double> %y) {
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entry:
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%div.i = fdiv <8 x double> %y, <double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00, double 4.500000e+00, double 3.400000e+00, double 2.300000e+00, double 1.200000e+00>
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ret <8 x double> %div.i
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}
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; CHECK-LABEL: divps512
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; CHECK: vdivps
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; CHECK: ret
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define <16 x float> @divps512(<16 x float> %y, <16 x float> %x) {
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entry:
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%div.i = fdiv <16 x float> %x, %y
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ret <16 x float> %div.i
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}
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; CHECK-LABEL: divps512fold
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; CHECK: vdivps LCP{{.*}}(%rip)
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; CHECK: ret
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define <16 x float> @divps512fold(<16 x float> %y) {
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entry:
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%div.i = fdiv <16 x float> %y, <float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 0x400B333340000000, float 0x4002666660000000, float 0x3FF3333340000000, float 4.500000e+00, float 4.500000e+00, float 0x4002666660000000, float 0x3FF3333340000000>
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ret <16 x float> %div.i
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}
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; CHECK-LABEL: vpaddq_test
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; CHECK: vpaddq %zmm
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; CHECK: ret
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define <8 x i64> @vpaddq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {
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%x = add <8 x i64> %i, %j
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vpaddd_test
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; CHECK: vpaddd %zmm
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; CHECK: ret
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define <16 x i32> @vpaddd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {
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%x = add <16 x i32> %i, %j
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpsubq_test
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; CHECK: vpsubq %zmm
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; CHECK: ret
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define <8 x i64> @vpsubq_test(<8 x i64> %i, <8 x i64> %j) nounwind readnone {
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%x = sub <8 x i64> %i, %j
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ret <8 x i64> %x
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}
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; CHECK-LABEL: vpsubd_test
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; CHECK: vpsubd
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; CHECK: ret
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define <16 x i32> @vpsubd_test(<16 x i32> %i, <16 x i32> %j) nounwind readnone {
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%x = sub <16 x i32> %i, %j
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ret <16 x i32> %x
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}
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; CHECK-LABEL: vpmulld_test
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; CHECK: vpmulld %zmm
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; CHECK: ret
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define <16 x i32> @vpmulld_test(<16 x i32> %i, <16 x i32> %j) {
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%x = mul <16 x i32> %i, %j
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ret <16 x i32> %x
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}
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; CHECK-LABEL: sqrtA
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; CHECK: vsqrtssz
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; CHECK: ret
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declare float @sqrtf(float) readnone
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define float @sqrtA(float %a) nounwind uwtable readnone ssp {
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entry:
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%conv1 = tail call float @sqrtf(float %a) nounwind readnone
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ret float %conv1
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}
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; CHECK-LABEL: sqrtB
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; CHECK: vsqrtsdz
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; CHECK: ret
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declare double @sqrt(double) readnone
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define double @sqrtB(double %a) nounwind uwtable readnone ssp {
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entry:
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%call = tail call double @sqrt(double %a) nounwind readnone
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ret double %call
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}
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; CHECK-LABEL: sqrtC
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; CHECK: vsqrtssz
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; CHECK: ret
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declare float @llvm.sqrt.f32(float)
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define float @sqrtC(float %a) nounwind {
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%b = call float @llvm.sqrt.f32(float %a)
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ret float %b
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}
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; CHECK-LABEL: fadd_broadcast
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; CHECK: LCP{{.*}}(%rip){1to16}, %zmm0, %zmm0
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; CHECK: ret
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define <16 x float> @fadd_broadcast(<16 x float> %a) nounwind {
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%b = fadd <16 x float> %a, <float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000, float 0x3FB99999A0000000>
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ret <16 x float> %b
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}
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; CHECK-LABEL: addq_broadcast
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; CHECK: vpaddq LCP{{.*}}(%rip){1to8}, %zmm0, %zmm0
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; CHECK: ret
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define <8 x i64> @addq_broadcast(<8 x i64> %a) nounwind {
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%b = add <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: orq_broadcast
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; CHECK: vporq LCP{{.*}}(%rip){1to8}, %zmm0, %zmm0
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; CHECK: ret
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define <8 x i64> @orq_broadcast(<8 x i64> %a) nounwind {
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%b = or <8 x i64> %a, <i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2, i64 2>
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ret <8 x i64> %b
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}
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; CHECK-LABEL: andd512fold
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; CHECK: vpandd (%
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; CHECK: ret
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define <16 x i32> @andd512fold(<16 x i32> %y, <16 x i32>* %x) {
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entry:
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%a = load <16 x i32>* %x, align 4
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%b = and <16 x i32> %y, %a
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ret <16 x i32> %b
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}
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; CHECK-LABEL: andqbrst
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; CHECK: vpandq (%rdi){1to8}, %zmm
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; CHECK: ret
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define <8 x i64> @andqbrst(<8 x i64> %p1, i64* %ap) {
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entry:
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%a = load i64* %ap, align 8
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%b = insertelement <8 x i64> undef, i64 %a, i32 0
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%c = shufflevector <8 x i64> %b, <8 x i64> undef, <8 x i32> zeroinitializer
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%d = and <8 x i64> %p1, %c
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ret <8 x i64>%d
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}
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