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https://github.com/RPCS3/llvm-mirror.git
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b2e5d643a8
Currently, llvm (backend) doesn't know cortex-r4, even though it is the default target for armv7r. Using "--target=armv7r-arm-none-eabi" provokes 'cortex-r4' is not a recognized processor for this target' by llvm. This patch adds support for cortex-r4 and, very closely related, r4f. llvm-svn: 234486
62 lines
1.7 KiB
LLVM
62 lines
1.7 KiB
LLVM
; RUN: llc -mtriple=thumb-apple-darwin -mcpu=arm1156t2-s -mattr=+thumb2 %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-THUMB
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; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-m3 -mattr=+thumb2 %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-THUMBV7M
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; RUN: llc -mtriple=thumb-apple-darwin -mcpu=swift %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
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; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4 %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
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; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r4f %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
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; RUN: llc -mtriple=thumb-apple-darwin -mcpu=cortex-r5 %s -o - \
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; RUN: | FileCheck %s -check-prefix=CHECK-HWDIV
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define i32 @f1(i32 %a, i32 %b) {
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entry:
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; CHECK-THUMB: f1
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; CHECK-THUMB: __divsi3
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; CHECK-THUMBV7M: f1
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; CHECK-THUMBV7M: sdiv
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; CHECK-HWDIV: f1
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; CHECK-HWDIV: sdiv
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%tmp1 = sdiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f2(i32 %a, i32 %b) {
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entry:
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; CHECK-THUMB: f2
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; CHECK-THUMB: __udivsi3
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; CHECK-THUMBV7M: f2
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; CHECK-THUMBV7M: udiv
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; CHECK-HWDIV: f2
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; CHECK-HWDIV: udiv
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%tmp1 = udiv i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f3(i32 %a, i32 %b) {
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entry:
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; CHECK-THUMB: f3
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; CHECK-THUMB: __modsi3
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; CHECK-THUMBV7M: f3
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; CHECK-THUMBV7M: sdiv
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; CHECK-HWDIV: f3
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; CHECK-HWDIV: sdiv
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%tmp1 = srem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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define i32 @f4(i32 %a, i32 %b) {
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entry:
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; CHECK-THUMB: f4
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; CHECK-THUMB: __umodsi3
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; CHECK-THUMBV7M: f4
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; CHECK-THUMBV7M: udiv
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; CHECK-HWDIV: f4
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; CHECK-HWDIV: udiv
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%tmp1 = urem i32 %a, %b ; <i32> [#uses=1]
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ret i32 %tmp1
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}
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