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https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
dd53274771
This reverts commit 80a34ae31125aa46dcad47162ba45b152aed968d with fixes. Previously, since bots turning on EXPENSIVE_CHECKS are essentially turning on MachineVerifierPass by default on X86 and the fact that inline-asm-avx-v-constraint-32bit.ll and inline-asm-avx512vl-v-constraint-32bit.ll are not expected to generate functioning machine code, this would go down to `report_fatal_error` in MachineVerifierPass. Here passing `-verify-machineinstrs=0` to make the intent explicit.
70 lines
2.9 KiB
LLVM
70 lines
2.9 KiB
LLVM
; Check that the CPU names work.
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; RUN: llc -mtriple=mips -mcpu=generic -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=GENERIC
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; GENERIC: ISA: MIPS32
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; RUN: llc -mtriple=mips -mcpu=mips2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS2
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; MIPS2: ISA: MIPS2
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; RUN: llc -mtriple=mips64 -mcpu=mips3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS3
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; MIPS3: ISA: MIPS3
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; RUN: llc -mtriple=mips64 -mcpu=mips4 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS4
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; MIPS4: ISA: MIPS4
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; RUN: llc -mtriple=mips -mcpu=mips32 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32
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; MIPS32: ISA: MIPS32
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; RUN: llc -mtriple=mips -mcpu=mips32r2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R2
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; MIPS32R2: ISA: MIPS32r2
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; RUN: llc -mtriple=mips -mcpu=mips32r3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R3
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; MIPS32R3: ISA: MIPS32r3
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; RUN: llc -mtriple=mips -mcpu=mips32r5 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R5
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; MIPS32R5: ISA: MIPS32r5
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; RUN: llc -mtriple=mips -mcpu=mips32r6 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS32R6
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; MIPS32R6: ISA: MIPS32r6
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; RUN: llc -mtriple=mips64 -mcpu=mips64 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64
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; MIPS64: ISA: MIPS64
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; RUN: llc -mtriple=mips64 -mcpu=mips64r2 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R2
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; MIPS64R2: ISA: MIPS64r2
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; RUN: llc -mtriple=mips64 -mcpu=mips64r3 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R3
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; MIPS64R3: ISA: MIPS64r3
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; RUN: llc -mtriple=mips64 -mcpu=mips64r5 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R5
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; MIPS64R5: ISA: MIPS64r5
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; RUN: llc -mtriple=mips64 -mcpu=mips64r6 -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=MIPS64R6
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; MIPS64R6: ISA: MIPS64r6
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; RUN: llc -mtriple=mips64 -mcpu=octeon -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=OCTEON
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; OCTEON: ISA: MIPS64r2
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; OCTEON: ISA Extension: Cavium Networks Octeon
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; RUN: llc -mtriple=mips64 -mcpu=octeon+ -filetype=obj < %s \
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; RUN: | llvm-readelf -A | FileCheck %s --check-prefix=OCTEONP
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; OCTEONP: ISA: MIPS64r2
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; OCTEONP: ISA Extension: Cavium Networks OcteonP
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; Check that we reject CPUs that are not implemented.
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; RUN: not --crash llc < %s -o /dev/null -mtriple=mips -mcpu=mips1 2>&1 \
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; RUN: | FileCheck %s --check-prefix=ERROR
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; RUN: not --crash llc < %s -o /dev/null -mtriple=mips64 -mcpu=mips5 2>&1 \
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; RUN: | FileCheck %s --check-prefix=ERROR
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; ERROR: LLVM ERROR: Code generation for MIPS-{{.}} is not implemented
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define void @foo() {
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ret void
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}
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