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https://github.com/RPCS3/llvm-mirror.git
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c43ce3d9fa
For multiprecision arithmetic on MIPS, rather than using ISD::ADDE / ISD::ADDC,
get SelectionDAG to break down the operation into ISD::ADDs and ISD::SETCCs.
For MIPS, only the DSP ASE has a carry flag, so in the general case it is not
useful to directly support ISD::{ADDE, ADDC, SUBE, SUBC} nodes.
Also improve the generation code in such cases for targets with
TargetLoweringBase::ZeroOrOneBooleanContent by directly using the result of the
comparison node rather than using it in selects. Similarly for ISD::SUBE /
ISD::SUBC.
Address optimization breakage by moving the generation of MIPS specific integer
multiply-accumulate nodes to before legalization.
This revolves PR32713 and PR33424.
Thanks to Simonas Kazlauskas and Pirama Arumuga Nainar for reporting the issue!
Reviewers: slthakur
Differential Revision: https://reviews.llvm.org/D33494
The previous version of this patch was too aggressive in producing fused
integer multiple-addition instructions.
llvm-svn: 307906
262 lines
7.2 KiB
LLVM
262 lines
7.2 KiB
LLVM
; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dsp < %s | FileCheck %s -check-prefix=R1
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; RUN: llc -march=mips -mcpu=mips32r2 -mattr=dspr2 < %s | FileCheck %s -check-prefix=R2
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; R1-LABEL: test_lbux:
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; R1: lbux ${{[0-9]+}}
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define zeroext i8 @test_lbux(i8* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i8, i8* %b, i32 %i
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%0 = load i8, i8* %add.ptr, align 1
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ret i8 %0
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}
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; R1-LABEL: test_lhx:
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; R1: lhx ${{[0-9]+}}
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define signext i16 @test_lhx(i16* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i16, i16* %b, i32 %i
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%0 = load i16, i16* %add.ptr, align 2
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ret i16 %0
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}
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; R1-LABEL: test_lwx:
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; R1: lwx ${{[0-9]+}}
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define i32 @test_lwx(i32* nocapture %b, i32 %i) {
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entry:
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%add.ptr = getelementptr inbounds i32, i32* %b, i32 %i
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%0 = load i32, i32* %add.ptr, align 4
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ret i32 %0
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}
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; R1-LABEL: test_add_v2q15_:
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; R1: addq.ph ${{[0-9]+}}
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define { i32 } @test_add_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%add = add <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %add to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: test_sub_v2q15_:
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; R1: subq.ph ${{[0-9]+}}
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define { i32 } @test_sub_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%sub = sub <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %sub to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R2-LABEL: test_mul_v2q15_:
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; R2: mul.ph ${{[0-9]+}}
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; mul.ph is an R2 instruction. Check that multiply node gets expanded.
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; R1-LABEL: test_mul_v2q15_:
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; R1: mul ${{[0-9]+}}
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; R1: mul ${{[0-9]+}}
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define { i32 } @test_mul_v2q15_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%1 = bitcast i32 %b.coerce to <2 x i16>
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%mul = mul <2 x i16> %0, %1
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%2 = bitcast <2 x i16> %mul to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: test_add_v4i8_:
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; R1: addu.qb ${{[0-9]+}}
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define { i32 } @test_add_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%add = add <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %add to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: test_sub_v4i8_:
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; R1: subu.qb ${{[0-9]+}}
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define { i32 } @test_sub_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%sub = sub <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %sub to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; DSP-ASE doesn't have a v4i8 multiply instruction. Check that multiply node gets expanded.
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; R2-LABEL: test_mul_v4i8_:
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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; R2: mul ${{[0-9]+}}
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define { i32 } @test_mul_v4i8_(i32 %a.coerce, i32 %b.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%1 = bitcast i32 %b.coerce to <4 x i8>
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%mul = mul <4 x i8> %0, %1
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%2 = bitcast <4 x i8> %mul to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %2, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: test_addsc:
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; R1: addsc ${{[0-9]+}}
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; R1: addwc ${{[0-9]+}}
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define i64 @test_addsc(i64 %a, i64 %b) {
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entry:
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%add = add nsw i64 %b, %a
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ret i64 %add
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}
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; R1-LABEL: shift1_v2i16_shl_:
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; R1: shll.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2i16_shl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shl = shl <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: shift1_v2i16_sra_:
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; R1: shra.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2i16_sra_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shr = ashr <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: shift1_v2ui16_srl_:
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; R1-NOT: shrl.ph
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; R2-LABEL: shift1_v2ui16_srl_:
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; R2: shrl.ph ${{[0-9]+}}, ${{[0-9]+}}, 15
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define { i32 } @shift1_v2ui16_srl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <2 x i16>
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%shr = lshr <2 x i16> %0, <i16 15, i16 15>
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%1 = bitcast <2 x i16> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: shift1_v4i8_shl_:
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; R1: shll.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4i8_shl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shl = shl <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: shift1_v4i8_sra_:
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; R1-NOT: shra.qb
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; R2-LABEL: shift1_v4i8_sra_:
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; R2: shra.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4i8_sra_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shr = ashr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; R1-LABEL: shift1_v4ui8_srl_:
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; R1: shrl.qb ${{[0-9]+}}, ${{[0-9]+}}, 7
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define { i32 } @shift1_v4ui8_srl_(i32 %a0.coerce) {
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entry:
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%0 = bitcast i32 %a0.coerce to <4 x i8>
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%shr = lshr <4 x i8> %0, <i8 7, i8 7, i8 7, i8 7>
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%1 = bitcast <4 x i8> %shr to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; Check that shift node is expanded if splat element size is not 16-bit.
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;
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; R1-LABEL: test_vector_splat_imm_v2q15:
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; R1-NOT: shll.ph
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define { i32 } @test_vector_splat_imm_v2q15(i32 %a.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%shl = shl <2 x i16> %0, <i16 0, i16 2>
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%1 = bitcast <2 x i16> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; Check that shift node is expanded if splat element size is not 8-bit.
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;
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; R1-LABEL: test_vector_splat_imm_v4i8:
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; R1-NOT: shll.qb
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define { i32 } @test_vector_splat_imm_v4i8(i32 %a.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%shl = shl <4 x i8> %0, <i8 0, i8 2, i8 0, i8 2>
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%1 = bitcast <4 x i8> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; Check that shift node is expanded if shift amount doesn't fit in 4-bit sa field.
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;
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; R1-LABEL: test_shift_amount_v2q15:
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; R1-NOT: shll.ph
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define { i32 } @test_shift_amount_v2q15(i32 %a.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <2 x i16>
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%shl = shl <2 x i16> %0, <i16 16, i16 16>
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%1 = bitcast <2 x i16> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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; Check that shift node is expanded if shift amount doesn't fit in 3-bit sa field.
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;
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; R1-LABEL: test_shift_amount_v4i8:
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; R1-NOT: shll.qb
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define { i32 } @test_shift_amount_v4i8(i32 %a.coerce) {
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entry:
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%0 = bitcast i32 %a.coerce to <4 x i8>
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%shl = shl <4 x i8> %0, <i8 8, i8 8, i8 8, i8 8>
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%1 = bitcast <4 x i8> %shl to i32
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%.fca.0.insert = insertvalue { i32 } undef, i32 %1, 0
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ret { i32 } %.fca.0.insert
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}
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