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llvm-mirror/test/MC/ARM/armv8a-fpmul-error.s
Bernard Ogden 1a1a8110d3 [ARM/AArch64] Support FP16 +fp16fml instructions
Add +fp16fml feature for new FP16 instructions, which are a
mandatory part of FP16 from v8.4-A and an optional part of FP16
from v8.2-A. It doesn't seem to be possible to model this in
LLVM, but the relationship between the options is handled by
the related clang patch.

In keeping with what I think is the usual practice, the fp16fml
extension is accepted regardless of base architecture version.

Builds on/replaces Sjoerd Meijer's patch to add these instructions at
https://reviews.llvm.org/D49839.

Differential Revision: https://reviews.llvm.org/D50228

llvm-svn: 340013
2018-08-17 11:29:49 +00:00

28 lines
1.1 KiB
ArmAsm

// RUN: not llvm-mc -triple arm -mattr=+fp16fml,+neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-ERROR
VFMAL.F16 D0, S1, S2[2]
vfmsl.f16 d0, s1, s2[2]
vfmsl.f16 d0, s1, s2[-1]
vfmal.f16 q0, d1, d2[4]
VFMSL.F16 Q0, D1, D2[4]
vfmal.f16 q0, d1, d2[-1]
//CHECK-ERROR: error: invalid operand for instruction
//CHECK-ERROR-NEXT: VFMAL.F16 D0, S1, S2[2]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[2]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmsl.f16 d0, s1, s2[-1]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[4]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: VFMSL.F16 Q0, D1, D2[4]
//CHECK-ERROR-NEXT: ^
//CHECK-ERROR-NEXT: error: invalid operand for instruction
//CHECK-ERROR-NEXT: vfmal.f16 q0, d1, d2[-1]
//CHECK-ERROR-NEXT: ^