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llvm-mirror/test/MC/X86
David Woodhouse a7b8d3d331 [x86] Fix retq/retl handling in 64-bit mode
This finishes the job started in r198756, and creates separate opcodes for
64-bit vs. 32-bit versions of the rest of the RET instructions too.

LRETL/LRETQ are interesting... I can't see any justification for their
existence in the SDM. There should be no 'LRETL' in 64-bit mode, and no
need for a REX.W prefix for LRETQ. But this is what GAS does, and my
Sandybridge CPU and an Opteron 6376 concur when tested as follows:

asm __volatile__("pushq $0x1234\nmovq $0x33,%rax\nsalq $32,%rax\norq $1f,%rax\npushq %rax\nlretl $8\n1:");
asm __volatile__("pushq $1234\npushq $0x33\npushq $1f\nlretq $8\n1:");
asm __volatile__("pushq $0x33\npushq $1f\nlretq\n1:");
asm __volatile__("pushq $0x1234\npushq $0x33\npushq $1f\nlretq $8\n1:");

cf. PR8592 and commit r118903, which added LRETQ. I only added LRETIQ to
match it.

I don't quite understand how the Intel syntax parsing for ret
instructions is working, despite r154468 allegedly fixing it. Aren't the
explicitly sized 'retw', 'retd' and 'retq' supposed to work? I have at
least made the 'lretq' work with (and indeed *require*) the 'q'.

llvm-svn: 199106
2014-01-13 14:05:59 +00:00
..
AlignedBundling [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
3DNow.s
2011-09-06-NoNewline.s
address-size.s [x86] Add basic support for .code16 2014-01-06 04:55:54 +00:00
avx512-encodings.s Add XOP disassembler support. Fixes PR13933. 2013-10-03 05:17:48 +00:00
cfi_def_cfa-crash.s X86: Assembly files with .cfi_cfa_def shouldn't hit llvm_unreachable() 2013-11-08 22:33:06 +00:00
fde-reloc.s
gnux32-dwarf-gen.s
intel-syntax-2.s
intel-syntax-directional-label.s Un-revert: the buildbot failure in LLVM on lld-x86_64-win7 had me with 2013-12-19 23:16:14 +00:00
intel-syntax-encoding.s
intel-syntax-hex.s
intel-syntax.s Fixing Intel format of the vshufpd instruction. 2013-09-27 01:44:23 +00:00
lit.local.cfg [tests] Cleanup initialization of test suffixes. 2013-08-16 00:37:11 +00:00
padlock.s
relax-insn.s [x86] Do not relax PUSHi16 to PUSHi32 (PR18414) 2014-01-08 12:58:32 +00:00
ret.s [x86] Fix retq/retl handling in 64-bit mode 2014-01-13 14:05:59 +00:00
shuffle-comments.s
stackmap-nops.ll Grow the stackmap/patchpoint format to hold 64-bit IDs. 2013-12-13 18:37:10 +00:00
x86_64-avx-clmul-encoding.s
x86_64-avx-encoding.s Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 2013-10-14 04:55:01 +00:00
x86_64-bmi-encoding.s
x86_64-encoding.s Allow pinsrw/pinsrb/pextrb/pextrw/movmskps/movmskpd/pmovmskb/extractps instructions to parse either GR32 or GR64 without resorting to duplicating instructions. 2013-10-14 04:55:01 +00:00
x86_64-fma3-encoding.s
x86_64-fma4-encoding.s
x86_64-hle-encoding.s
x86_64-imm-widths.s
x86_64-rand-encoding.s
x86_64-rtm-encoding.s
x86_64-sse4a.s
x86_64-tbm-encoding.s Adding intrinsics to the llvm backend for TBM instruction set. 2013-09-27 18:38:42 +00:00
x86_64-xop-encoding.s
x86_directives.s
x86_errors.s [x86] Make AsmParser validate registers for memory operands a bit better 2014-01-08 12:58:28 +00:00
x86_long_nop.s
x86_nop.s Use -triple to fix the test on non-ELF hosts. 2013-11-25 20:46:18 +00:00
x86_operands.s
x86-16.s [x86] Fix MOV8ao8 et al for 16-bit mode, fix up disassembler to understand 2014-01-08 12:58:24 +00:00
x86-32-avx.s
x86-32-coverage.s
x86-32-fma3.s
x86-32-ms-inline-asm.s
x86-32.s [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases 2014-01-08 12:57:55 +00:00
x86-64.s [x86] Disambiguate [LS][IG]DT{32,64}m and add 16-bit versions, fix aliases 2014-01-08 12:57:55 +00:00
x86-target-directives.s correct target directive handling error handling 2014-01-13 01:15:39 +00:00