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a7e76895fa
This commit serializes machine basic block operands. The machine basic block operands use the following syntax: %bb.<id>[.<name>] This commit also modifies the YAML representation for the machine basic blocks - a new, required field 'id' is added to the MBB YAML mapping. The id is used to resolve the MBB references to the actual MBBs. And while the name of the MBB can be included in a MBB reference, this name isn't used to resolve MBB references - as it's possible that multiple MBBs will reference the same BB and thus they will have the same name. If the name is specified, the parser will verify that it is equal to the name of the MBB with the specified id. Reviewers: Duncan P. N. Exon Smith Differential Revision: http://reviews.llvm.org/D10608 llvm-svn: 240792
130 lines
3.7 KiB
C++
130 lines
3.7 KiB
C++
//===- MIRYAMLMapping.h - Describes the mapping between MIR and YAML ------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// The MIR serialization library is currently a work in progress. It can't
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// serialize machine functions at this time.
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//
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// This file implements the mapping between various MIR data structures and
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// their corresponding YAML representation.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
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#define LLVM_LIB_CODEGEN_MIRYAMLMAPPING_H
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#include "llvm/ADT/StringRef.h"
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#include "llvm/Support/YAMLTraits.h"
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#include <vector>
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namespace llvm {
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namespace yaml {
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/// A wrapper around std::string which contains a source range that's being
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/// set during parsing.
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struct StringValue {
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std::string Value;
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SMRange SourceRange;
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StringValue() {}
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StringValue(std::string Value) : Value(std::move(Value)) {}
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bool operator==(const StringValue &Other) const {
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return Value == Other.Value;
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}
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};
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template <> struct ScalarTraits<StringValue> {
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static void output(const StringValue &S, void *, llvm::raw_ostream &OS) {
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OS << S.Value;
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}
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static StringRef input(StringRef Scalar, void *Ctx, StringValue &S) {
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S.Value = Scalar.str();
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if (const auto *Node =
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reinterpret_cast<yaml::Input *>(Ctx)->getCurrentNode())
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S.SourceRange = Node->getSourceRange();
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return "";
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}
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static bool mustQuote(StringRef Scalar) { return needsQuotes(Scalar); }
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};
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} // end namespace yaml
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} // end namespace llvm
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LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::StringValue)
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namespace llvm {
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namespace yaml {
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struct MachineBasicBlock {
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unsigned ID;
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std::string Name;
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unsigned Alignment = 0;
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bool IsLandingPad = false;
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bool AddressTaken = false;
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// TODO: Serialize the successors and liveins.
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std::vector<StringValue> Instructions;
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};
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template <> struct MappingTraits<MachineBasicBlock> {
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static void mapping(IO &YamlIO, MachineBasicBlock &MBB) {
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YamlIO.mapRequired("id", MBB.ID);
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YamlIO.mapOptional("name", MBB.Name,
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std::string()); // Don't print out an empty name.
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YamlIO.mapOptional("alignment", MBB.Alignment);
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YamlIO.mapOptional("isLandingPad", MBB.IsLandingPad);
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YamlIO.mapOptional("addressTaken", MBB.AddressTaken);
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YamlIO.mapOptional("instructions", MBB.Instructions);
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::MachineBasicBlock)
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namespace llvm {
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namespace yaml {
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struct MachineFunction {
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StringRef Name;
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unsigned Alignment = 0;
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bool ExposesReturnsTwice = false;
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bool HasInlineAsm = false;
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// Register information
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bool IsSSA = false;
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bool TracksRegLiveness = false;
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bool TracksSubRegLiveness = false;
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// TODO: Serialize virtual register definitions.
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// TODO: Serialize the various register masks.
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// TODO: Serialize live in registers.
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std::vector<MachineBasicBlock> BasicBlocks;
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};
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template <> struct MappingTraits<MachineFunction> {
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static void mapping(IO &YamlIO, MachineFunction &MF) {
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YamlIO.mapRequired("name", MF.Name);
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YamlIO.mapOptional("alignment", MF.Alignment);
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YamlIO.mapOptional("exposesReturnsTwice", MF.ExposesReturnsTwice);
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YamlIO.mapOptional("hasInlineAsm", MF.HasInlineAsm);
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YamlIO.mapOptional("isSSA", MF.IsSSA);
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YamlIO.mapOptional("tracksRegLiveness", MF.TracksRegLiveness);
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YamlIO.mapOptional("tracksSubRegLiveness", MF.TracksSubRegLiveness);
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YamlIO.mapOptional("body", MF.BasicBlocks);
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}
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};
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} // end namespace yaml
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} // end namespace llvm
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#endif
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