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03e283a2c0
Currently aarch64-ldst-opt will incorrectly rename registers with multiple disjunct subregisters (e.g. result of LD3). This patch updates the canRenameUpToDef to bail out if it encounters such a register class that contains the register to rename. Fixes PR46105. Reviewers: efriedma, dmgreen, paquette, t.p.northover Reviewed By: efriedma Differential Revision: https://reviews.llvm.org/D81108
41 lines
1.6 KiB
YAML
41 lines
1.6 KiB
YAML
# RUN: llc -run-pass=aarch64-ldst-opt -mtriple=arm64-apple-iphoneos -aarch64-load-store-renaming=true -o - -verify-machineinstrs %s | FileCheck %s
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--- |
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define void @test_ld3(<8 x i8>* %a1) {
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entry:
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%s1 = alloca i64
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ret void
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}
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...
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---
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# CHECK-LABEL: name: test_ld3
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# CHECK: bb.0.entry:
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# CHECK: renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
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# CHECK-NEXT: STPDi renamable $d0, renamable $d1, $fp, -6 :: (store 8)
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# CHECK-NEXT: STURDi renamable $d2, $fp, -32, implicit killed $d0_d1_d2 :: (store 8 into %ir.s1)
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# CHECK-NEXT: renamable $d0_d1_d2 = LD3Threev8b killed renamable $x0 :: (load 24 from %ir.a1, align 32)
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# CHECK-NEXT: STPDi renamable $d0, renamable $d1, $fp, -3 :: (store 8)
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# CHECK-NEXT: STURDi renamable $d2, $fp, -8, implicit killed $d0_d1_d2 :: (store 8)
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# CHECK-NEXT: RET undef $lr
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#
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name: test_ld3
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alignment: 4
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tracksRegLiveness: true
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frameInfo: {}
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machineFunctionInfo: {}
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body: |
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bb.0.entry:
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liveins: $x0, $x1, $lr, $fp
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renamable $x0, renamable $d0_d1_d2 = LD3Threev8b_POST killed renamable $x0, $xzr
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STURDi renamable $d0, $fp, -48 :: (store 8)
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STURDi renamable $d1, $fp, -40 :: (store 8)
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STURDi renamable $d2, $fp, -32, implicit killed $d0_d1_d2 :: (store 8 into %ir.s1)
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renamable $d0_d1_d2 = LD3Threev8b killed renamable $x0 :: (load 24 from %ir.a1, align 32)
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STURDi renamable $d0, $fp, -24 :: (store 8)
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STURDi renamable $d1, $fp, -16 :: (store 8)
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STURDi renamable $d2, $fp, -8, implicit killed $d0_d1_d2 :: (store 8)
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RET undef $lr
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...
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