mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-10-22 20:43:44 +02:00
ce011a4aed
This makes the createGenericSchedLive() function that constructs the
default scheduler available for the public API. This should help when
you want to get a scheduler and the default list of DAG mutations.
This also shrinks the list of default DAG mutations:
{Load|Store}ClusterDAGMutation and MacroFusionDAGMutation are no longer
added by default. Targets can easily add them if they need them. It also
makes it easier for targets to add alternative/custom macrofusion or
clustering mutations while staying with the default
createGenericSchedLive(). It also saves the callback back and forth in
TargetInstrInfo::enableClusterLoads()/enableClusterStores().
Differential Revision: https://reviews.llvm.org/D26986
llvm-svn: 288057
58 lines
1.8 KiB
C++
58 lines
1.8 KiB
C++
//===-- AMDGPUInstrInfo.h - AMDGPU Instruction Information ------*- C++ -*-===//
|
|
//
|
|
// The LLVM Compiler Infrastructure
|
|
//
|
|
// This file is distributed under the University of Illinois Open Source
|
|
// License. See LICENSE.TXT for details.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
//
|
|
/// \file
|
|
/// \brief Contains the definition of a TargetInstrInfo class that is common
|
|
/// to all AMD GPUs.
|
|
//
|
|
//===----------------------------------------------------------------------===//
|
|
|
|
#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
|
|
#define LLVM_LIB_TARGET_AMDGPU_AMDGPUINSTRINFO_H
|
|
|
|
#include "llvm/Target/TargetInstrInfo.h"
|
|
#include "Utils/AMDGPUBaseInfo.h"
|
|
|
|
#define GET_INSTRINFO_HEADER
|
|
#define GET_INSTRINFO_ENUM
|
|
#include "AMDGPUGenInstrInfo.inc"
|
|
|
|
namespace llvm {
|
|
|
|
class AMDGPUSubtarget;
|
|
class MachineFunction;
|
|
class MachineInstr;
|
|
class MachineInstrBuilder;
|
|
|
|
class AMDGPUInstrInfo : public AMDGPUGenInstrInfo {
|
|
private:
|
|
const AMDGPUSubtarget &ST;
|
|
|
|
virtual void anchor();
|
|
|
|
public:
|
|
explicit AMDGPUInstrInfo(const AMDGPUSubtarget &st);
|
|
|
|
bool shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
|
|
int64_t Offset1, int64_t Offset2,
|
|
unsigned NumLoads) const override;
|
|
|
|
/// \brief Return a target-specific opcode if Opcode is a pseudo instruction.
|
|
/// Return -1 if the target-specific opcode for the pseudo instruction does
|
|
/// not exist. If Opcode is not a pseudo instruction, this is identity.
|
|
int pseudoToMCOpcode(int Opcode) const;
|
|
|
|
/// \brief Given a MIMG \p Opcode that writes all 4 channels, return the
|
|
/// equivalent opcode that writes \p Channels Channels.
|
|
int getMaskedMIMGOp(uint16_t Opcode, unsigned Channels) const;
|
|
};
|
|
} // End llvm namespace
|
|
|
|
#endif
|