mirror of
https://github.com/RPCS3/llvm-mirror.git
synced 2024-11-23 11:13:28 +01:00
5962b8bbf7
Additionally, allow more than two operands to !con, !add, !and, !or in the same way as is already allowed for !listconcat and !strconcat. Change-Id: I9659411f554201b90cd8ed7c7e004d381a66fa93 Differential revision: https://reviews.llvm.org/D44112 llvm-svn: 327494
26 lines
708 B
TableGen
26 lines
708 B
TableGen
// RUN: llvm-tblgen %s | FileCheck %s
|
|
// XFAIL: vg_leak
|
|
|
|
// CHECK: --- Defs ---
|
|
|
|
// CHECK: def A0 {
|
|
// CHECK: bits<8> add = { 0, 1, 0, 0, 0, 0, 0, 0 };
|
|
// CHECK: bits<8> and = { 0, 0, 0, 0, 0, 0, 0, 1 };
|
|
// CHECK: bits<8> or = { 0, 0, 1, 1, 1, 1, 1, 1 };
|
|
// CHECK: bits<8> srl = { 0, 0, 0, 1, 1, 1, 1, 1 };
|
|
// CHECK: bits<8> sra = { 0, 0, 0, 1, 1, 1, 1, 1 };
|
|
// CHECK: bits<8> shl = { 0, 1, 1, 1, 1, 1, 1, 0 };
|
|
// CHECK: }
|
|
|
|
class A<bits<8> a, bits<2> b> {
|
|
// Operands of different bits types are allowed.
|
|
bits<8> add = !add(a, b);
|
|
bits<8> and = !and(a, b);
|
|
bits<8> or = !or(a, b);
|
|
bits<8> srl = !srl(a, b);
|
|
bits<8> sra = !sra(a, b);
|
|
bits<8> shl = !shl(a, b);
|
|
}
|
|
|
|
def A0 : A<63, 1>;
|