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e3e67d4a0a
This changes the SelectionDAG scheduling preference to source order. Soon, the SelectionDAG scheduler can be bypassed saving a nice chunk of compile time. Performance differences that result from this change are often a consequence of register coalescing. The register coalescer is far from perfect. Bugs can be filed for deficiencies. On x86 SandyBridge/Haswell, the source order schedule is often preserved, particularly for small blocks. Register pressure is generally improved over the SD scheduler's ILP mode. However, we are still able to handle large blocks that require latency hiding, unlike the SD scheduler's BURR mode. MI scheduler also attempts to discover the critical path in single-block loops and adjust heuristics accordingly. The MI scheduler relies on the new machine model. This is currently unimplemented for AVX, so we may not be generating the best code yet. Unit tests are updated so they don't depend on SD scheduling heuristics. llvm-svn: 192750
196 lines
5.2 KiB
LLVM
196 lines
5.2 KiB
LLVM
; RUN: llc < %s -mattr=+sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Darwin
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; RUN: llc < %s -mattr=+sse2 -mtriple=i686-pc-mingw32 -mcpu=core2 | FileCheck %s -check-prefix=SSE2-Mingw32
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; RUN: llc < %s -mattr=+sse,-sse2 -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=SSE1
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; RUN: llc < %s -mattr=-sse -mtriple=i686-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=NOSSE
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; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=core2 | FileCheck %s -check-prefix=X86-64
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@.str = internal constant [25 x i8] c"image\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00\00"
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@.str2 = internal constant [30 x i8] c"xxxxxxxxxxxxxxxxxxxxxxxxxxxxx\00", align 4
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define void @t1(i32 %argc, i8** %argv) nounwind {
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entry:
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; SSE2-Darwin-LABEL: t1:
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; SSE2-Darwin: movsd _.str+16, %xmm0
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; SSE2-Darwin: movsd %xmm0, 16(%esp)
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; SSE2-Darwin: movaps _.str, %xmm0
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; SSE2-Darwin: movaps %xmm0
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; SSE2-Darwin: movb $0, 24(%esp)
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; SSE2-Mingw32-LABEL: t1:
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; SSE2-Mingw32: movsd _.str+16, %xmm0
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; SSE2-Mingw32: movsd %xmm0, 16(%esp)
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; SSE2-Mingw32: movaps _.str, %xmm0
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; SSE2-Mingw32: movups %xmm0
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; SSE2-Mingw32: movb $0, 24(%esp)
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; SSE1-LABEL: t1:
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; SSE1: movaps _.str, %xmm0
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; SSE1: movaps %xmm0
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; SSE1: movb $0, 24(%esp)
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; SSE1: movl $0, 20(%esp)
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; SSE1: movl $0, 16(%esp)
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; NOSSE-LABEL: t1:
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; NOSSE: movb $0
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; NOSSE: movl $0
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; NOSSE: movl $0
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; NOSSE: movl $0
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; NOSSE: movl $0
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; NOSSE: movl $101
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; NOSSE: movl $1734438249
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; X86-64-LABEL: t1:
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; X86-64: movaps _.str(%rip), %xmm0
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; X86-64: movaps %xmm0
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; X86-64: movb $0
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; X86-64: movq $0
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%tmp1 = alloca [25 x i8]
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%tmp2 = bitcast [25 x i8]* %tmp1 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([25 x i8]* @.str, i32 0, i32 0), i32 25, i32 1, i1 false)
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unreachable
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}
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;rdar://7774704
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%struct.s0 = type { [2 x double] }
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define void @t2(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
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entry:
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; SSE2-Darwin-LABEL: t2:
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; SSE2-Darwin: movaps (%ecx), %xmm0
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; SSE2-Darwin: movaps %xmm0, (%eax)
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; SSE2-Mingw32-LABEL: t2:
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; SSE2-Mingw32: movaps (%ecx), %xmm0
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; SSE2-Mingw32: movaps %xmm0, (%eax)
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; SSE1-LABEL: t2:
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; SSE1: movaps (%ecx), %xmm0
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; SSE1: movaps %xmm0, (%eax)
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; NOSSE-LABEL: t2:
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; X86-64-LABEL: t2:
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; X86-64: movaps (%rsi), %xmm0
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; X86-64: movaps %xmm0, (%rdi)
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%tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1]
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%tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1]
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 16, i1 false)
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ret void
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}
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define void @t3(%struct.s0* nocapture %a, %struct.s0* nocapture %b) nounwind ssp {
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entry:
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; SSE2-Darwin-LABEL: t3:
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; SSE2-Darwin: movsd (%ecx), %xmm0
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; SSE2-Darwin: movsd 8(%ecx), %xmm1
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; SSE2-Darwin: movsd %xmm1, 8(%eax)
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; SSE2-Darwin: movsd %xmm0, (%eax)
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; SSE2-Mingw32-LABEL: t3:
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; SSE2-Mingw32: movsd (%ecx), %xmm0
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; SSE2-Mingw32: movsd 8(%ecx), %xmm1
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; SSE2-Mingw32: movsd %xmm1, 8(%eax)
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; SSE2-Mingw32: movsd %xmm0, (%eax)
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; SSE1-LABEL: t3:
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; SSE1: movl
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; NOSSE-LABEL: t3:
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; NOSSE: movl
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; X86-64-LABEL: t3:
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; X86-64: movq (%rsi), %rax
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; X86-64: movq 8(%rsi), %rcx
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; X86-64: movq %rcx, 8(%rdi)
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; X86-64: movq %rax, (%rdi)
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%tmp2 = bitcast %struct.s0* %a to i8* ; <i8*> [#uses=1]
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%tmp3 = bitcast %struct.s0* %b to i8* ; <i8*> [#uses=1]
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tail call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* %tmp3, i32 16, i32 8, i1 false)
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ret void
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}
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define void @t4() nounwind {
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entry:
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; SSE2-Darwin-LABEL: t4:
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; SSE2-Darwin: movw $120
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Darwin: movl $2021161080
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; SSE2-Mingw32-LABEL: t4:
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; SSE2-Mingw32: movw $120
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE2-Mingw32: movl $2021161080
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; SSE1-LABEL: t4:
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; SSE1: movw $120
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; SSE1: movl $2021161080
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; NOSSE-LABEL: t4:
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; NOSSE: movw $120
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; NOSSE: movl $2021161080
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; X86-64-LABEL: t4:
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; X86-64: movabsq $8680820740569200760, %rax
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; X86-64: movq %rax
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; X86-64: movq %rax
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; X86-64: movq %rax
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; X86-64: movw $120
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; X86-64: movl $2021161080
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%tmp1 = alloca [30 x i8]
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%tmp2 = bitcast [30 x i8]* %tmp1 to i8*
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call void @llvm.memcpy.p0i8.p0i8.i32(i8* %tmp2, i8* getelementptr inbounds ([30 x i8]* @.str2, i32 0, i32 0), i32 30, i32 1, i1 false)
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unreachable
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}
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declare void @llvm.memcpy.p0i8.p0i8.i32(i8* nocapture, i8* nocapture, i32, i32, i1) nounwind
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